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Clock Domain

Concept WIKI v1 · 6/9/2026

A clock domain is a region of a digital circuit in which all sequential elements are clocked by a single, related clock signal. In modern System-on-Chip (SoC) designs, multiple asynchronous clock domains coexist, requiring explicit handling of clock domain crossings (CDC) to avoid metastability and functional bugs.

Definition

A clock domain is a portion of a synchronous digital circuit in which every flip-flop, register, and other clocked storage element is driven by (or derived from) the same clock signal. Signals that originate in one clock domain and are consumed in another must traverse a clock domain crossing (CDC), which is susceptible to metastability if not properly synchronized.

In the rtlv case study of the MicroTitan RISC-V SoC, the authors state that "MicroTitan includes multiple clock domains that we verified separately", and the paper focuses its detailed analysis on the core clock domain.

Composition of a Clock Domain

A clock domain groups together the hardware blocks that share a common time base. In MicroTitan, the core clock domain contains:

  • The Ibex CPU core
  • On-chip memories (8 KB ROM and 8 KB RAM)
  • The UART peripheral
  • Slices of the SPI and USB peripherals

Peripherals split across clock domains (e.g., SPI and USB) have portions in multiple domains, with CDC paths between them.

Clock Domain Crossings (CDC)

When an SoC is partitioned into multiple clock domains, signals crossing between them are CDC paths. The arxiv survey Pragmatic Formal Verification Methodology for Clock Domain Crossing (CDC) notes:

  • "SoC designs often operate on multiple asynchronous clock domains, further adding to the complexity of the overall design."
  • To save power, designers adopt a Globally-Asynchronous Locally-Synchronous (GALS) approach, in which each clock domain is locally synchronous but globally asynchronous with respect to its neighbors.
  • CDC paths are "prone to metastability effects", and conventional RTL simulation and static timing analysis are insufficient to fully verify them, leading to verification gaps and potentially costly silicon re-spins.

A clock domain transfer circuit in the on-chip link synchronizer paper transfers sampled data from the link's recovered clock domain into the receiver's system clock domain, with a maximum latency of three clock cycles.

Verification Considerations

Because each clock domain is locally synchronous, it can in principle be verified as an independent synchronous circuit. In the rtlv work, the authors verify the properties of MicroTitan's clock domains separately and then reason about how the individual results imply a top-level property; they note the absence of a "machine-checked, end-to-end proof that these individual properties imply a top-level output determinism property."

Verification tools impose some restrictions on how clock domains can be modeled. The rtlv paper reports the following limitations relevant to clock domains:

  • Combinational latches are not supported, although this is rarely limiting for FPGA-targeted designs.
  • Asynchronous resets are not supported.
  • Clocks derived from logic in Verilog are not supported; such structures must be removed, transformed, or preprocessed using Yosys's clk2fflogic pass to produce a circuit model that the tool can handle.

See Also

  • MicroTitan — the RISC-V SoC case study in which multiple clock domains are separately verified.
  • Clock domain crossing (CDC) — the interface between two clock domains.
  • Metastability — the failure mode that synchronization at CDC paths must guard against.
  • GALS (Globally-Asynchronous Locally-Synchronous) — a design style in which locally synchronous clock domains communicate asynchronously.

LINKED ENTITIES

1 links
MicroTitan PART_OF

CITATIONS

6 sources
6 citations
[1] MicroTitan includes multiple clock domains that were verified separately, with the case study focusing on the core clock domain. rtlv: push-button verification of software on hardware
[2] The core clock domain of MicroTitan contains the Ibex CPU, memories, UART, and slices of the SPI and USB peripherals. rtlv: push-button verification of software on hardware
[3] MicroTitan's other clock domains were also verified, but no machine-checked end-to-end proof ties the per-domain properties to a top-level output determinism property. rtlv: push-button verification of software on hardware
[4] rtlv does not support asynchronous resets or clocks derived from logic in Verilog; these can be removed, transformed, or preprocessed using Yosys's clk2fflogic pass. rtlv: push-button verification of software on hardware
[5] Modern SoC designs often operate on multiple asynchronous clock domains, and a GALS approach is commonly used to create multiple asynchronous domains, with CDC paths prone to metastability. Pragmatic Formal Verification Methodology for Clock Domain Crossing (CDC)
[6] A clock domain transfer circuit can move sampled data from one clock domain to a receiver clock domain with a maximum latency of three clock cycles. A Clock Synchronizer for Repeaterless Low Swing On-Chip Links