Jonathan Woodruff
PersonJonathan Woodruff is documented in the provided evidence as a co-author of the 2023 IEEE Design & Test paper "Randomized Testing of RISC-V CPUs using Direct Instruction Injection," which presents TestRIG, a randomized testing framework for RISC-V implementations.
First seen 5/27/2026
Last seen 6/9/2026
Evidence 3 chunks
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WIKI
Overview
Jonathan Woodruff is listed as one of the authors of the paper "Randomized Testing of RISC-V CPUs using Direct Instruction Injection", published in IEEE Design & Test in 2023. The author list includes Alexandre Joannou, Peter Rugg, Jonathan Woodruff, Franz A. Fuchs, Marno van der Maas, Matthew Naylor, Michael Roe, Robert N. M. Watson, Peter G. Neumann, and Simon W. Moore.
Documented technical work
NEIGHBORHOOD
2 nodes · 1 edgesgraph · Jonathan Woodruff · depth=1
RELATIONSHIPS
2 connectionsJonathan Woodruff is listed as an author of the paper.
Jonathan Woodruff is listed as an author of the paper.
CITATIONS
4 sources4 citations — click to collapse
[1] Jonathan Woodruff is listed as an author of "Randomized Testing of RISC-V CPUs using Direct Instruction Injection." Randomized Testing of RISC-V CPUs using Direct Instruction Injection
[2] The paper is identified in the evidence as an IEEE Design & Test 2023 publication. Randomized Testing of RISC-V CPUs using Direct Instruction Injection
[3] The paper describes TestRIG as a RISC-V testing framework that generates random instruction sequences, executes them on a model and an implementation under test, and compares execution traces. Randomized Testing of RISC-V CPUs using Direct Instruction Injection
[4] The paper describes Direct Instruction Injection as supplying the next instruction from the test harness regardless of the CPU program counter, and states that TestRIG uses RVFI to observe post-instruction state changes. Randomized Testing of RISC-V CPUs using Direct Instruction Injection