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Jonathan Woodruff

Person WIKI v1 · 5/27/2026

Jonathan Woodruff is documented in the provided evidence as a co-author of the 2023 IEEE Design & Test paper "Randomized Testing of RISC-V CPUs using Direct Instruction Injection," which presents TestRIG, a randomized testing framework for RISC-V implementations.

Overview

Jonathan Woodruff is listed as one of the authors of the paper "Randomized Testing of RISC-V CPUs using Direct Instruction Injection", published in IEEE Design & Test in 2023. The author list includes Alexandre Joannou, Peter Rugg, Jonathan Woodruff, Franz A. Fuchs, Marno van der Maas, Matthew Naylor, Michael Roe, Robert N. M. Watson, Peter G. Neumann, and Simon W. Moore.

Documented technical work

The provided evidence connects Woodruff to work on TestRIG, short for Testing with Random Instruction Generation. The paper describes TestRIG as a testing framework for RISC-V implementations that compares an implementation under test with a formal or executable model by generating random instruction sequences, executing the same sequences on both systems, and comparing execution traces.

The paper also describes Direct Instruction Injection (DII), a technique in which the next instruction to execute is supplied by the test harness rather than fetched normally from program memory according to the program counter. In the described workflow, TestRIG uses the RISC-V Formal Interface (RVFI) to observe state changes after each instruction.

Scope of evidence

The supplied evidence supports Woodruff's authorship of the TestRIG paper and the paper's technical subject matter. It does not provide independent biographical details, institutional affiliation, education, or a distinct individual role within the project.

LINKED ENTITIES

1 links
Randomized Testing of RISC-V CPUs using Direct Instruction Injection AUTHORED_BY

CITATIONS

4 sources
4 citations
[1] Jonathan Woodruff is listed as an author of "Randomized Testing of RISC-V CPUs using Direct Instruction Injection." Randomized Testing of RISC-V CPUs using Direct Instruction Injection
[2] The paper is identified in the evidence as an IEEE Design & Test 2023 publication. Randomized Testing of RISC-V CPUs using Direct Instruction Injection
[3] The paper describes TestRIG as a RISC-V testing framework that generates random instruction sequences, executes them on a model and an implementation under test, and compares execution traces. Randomized Testing of RISC-V CPUs using Direct Instruction Injection
[4] The paper describes Direct Instruction Injection as supplying the next instruction from the test harness regardless of the CPU program counter, and states that TestRIG uses RVFI to observe post-instruction state changes. Randomized Testing of RISC-V CPUs using Direct Instruction Injection