Franz A. Fuchs

Person

Franz A. Fuchs is a researcher at the University of Cambridge associated with the TestRIG randomized testing framework for RISC-V CPUs. He is a co-author of the IEEE Design & Test 2024 paper 'Randomized Testing of RISC-V CPUs Using Direct Instruction Injection' and of the 2025 RISC-V Summit Europe presentation 'Who tests the TestRIG? Tooling for randomised tandem verification', both of which develop tools for cross-verifying RISC-V implementations, with a particular focus on the CHERI-enabled Toooba processor.

First seen 5/27/2026

Last seen 6/9/2026

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Overview

Franz A. Fuchs is a researcher affiliated with the University of Cambridge (Department of Computer Science and Technology, cl.cam.ac.uk) who works on randomized and mutation-based testing of RISC-V CPUs, with a particular emphasis on the CHERI capability-security extensions. He is listed as a co-author of the journal paper "Randomized Testing of RISC-V CPUs Using Direct Instruction Injection", published in IEEE Design & Test, volume 41, issue 1, pages 40–49, in February 2024 (DOI: 10.1109/MDAT.2023.3262741). The full author list is: Alexandre Joannou, Peter Rugg, Jonathan Woodruff, Franz A. Fuchs, Marno van der Maas, Matthew Naylor, Michael Roe, Robert N. M. Watson, Peter G. Neumann, and Simon W. Moore.

Fuchs is also a co-author of the RISC-V Summit Europe 2025 presentation "Who tests the TestRIG? Tooling for randomised tandem verification" (Peter Rugg, Alexandre Joannou, Jonathan Woodruff, Franz A. Fuchs, Simon W. Moore).

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Randomized Testing of RISC-V CPUs using Direct Instruction Injection ← authored by 100% 6e

Franz A. Fuchs is listed as an author of the paper.

Who tests the TestRIG? Tooling for randomised tandem verification ← authored by 100% 1e

Franz A. Fuchs is listed as an author of the paper.

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Randomized Testing of RISC-V CPUs using Direct Instruction Injection AUTHORED_BY Extracted graph relationship

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[1] Franz A. Fuchs is a co-author of the paper 'Randomized Testing of RISC-V CPUs Using Direct Instruction Injection', published in IEEE Design & Test, 41(1):40-49, February 2024 (DOI: 10.1109/MDAT.2023.3262741), with co-authors Alexandre Joannou, Peter Rugg, Jonathan Woodruff, Marno van der Maas, Matthew Naylor, Michael Roe, Robert N. M. Watson, Peter G. Neumann, and Simon W. Moore. Randomized Testing of RISC-V CPUs Using Direct Instruction Injection - researchr publication

[2] Franz A. Fuchs is a co-author of the RISC-V Summit Europe 2025 presentation 'Who tests the TestRIG? Tooling for randomised tandem verification' (Peter Rugg, Alexandre Joannou, Jonathan Woodruff, Franz A. Fuchs, Simon W. Moore, University of Cambridge), which discusses mutation-based coverage tooling, static test suite generation, and a single-implementation fuzzing mode for TestRIG, motivated by testing the Toooba processor with CHERI security extensions. Who tests the TestRIG? Tooling for randomised tandem verification (RISC-V Summit Europe 2025)

[3] TestRIG (Testing with Random Instruction Generation) is a framework that cross-verifies RISC-V implementations against the Sail formal model by generating random instruction sequences, executing them in tandem on the model and the implementation, and comparing execution traces; it does not prove equivalence but can demonstrate divergence, and is usable at all stages of development. Randomized Testing of RISC-V CPUs using Direct Instruction Injection (preprint PDF, CTSRD)

[4] Direct Instruction Injection (DII) is a test-injection technique in which the next instruction to be executed is provided directly by the test harness regardless of the program counter, complementing the RISC-V Formal Interface (RVFI) used to observe per-instruction state changes. Randomized Testing of RISC-V CPUs using Direct Instruction Injection (preprint PDF, CTSRD)

[5] The authors used TestRIG to test many standard RISC-V extensions and the experimental CHERI security extension, and report that it replaced instruction-set level unit testing because it was easier to use, gave more thorough coverage through random generation, and was effective at detecting issues in instruction semantics, the pipeline, and data caches. Randomized Testing of RISC-V CPUs using Direct Instruction Injection (preprint PDF, CTSRD)

[6] The 2025 RISC-V Summit Europe work describes mutation-based coverage tooling for the Sail CHERI golden model, features for generating static test suites, and a single-implementation fuzzing mode, with motivation from testing the Toooba processor including its CHERI extensions, and notes community engagement from Microsoft Research, lowRISC, and SCI Semiconductor. Who tests the TestRIG? Tooling for randomised tandem verification (RISC-V Summit Europe 2025)

[7] TestRIG includes a QuickCheckVEngine verification engine that uses Haskell's QuickCheck library to generate tests and automatically shrink divergences to minimal reproducers, and connects to implementations via the standardized RVFI-DII interface implemented by the Sail golden RISC-V model. Who tests the TestRIG? Tooling for randomised tandem verification (RISC-V Summit Europe 2025)