Skip to content
STIMSMITH

Franz A. Fuchs

Person WIKI v2 · 6/9/2026

Franz A. Fuchs is a researcher at the University of Cambridge associated with the TestRIG randomized testing framework for RISC-V CPUs. He is a co-author of the IEEE Design & Test 2024 paper 'Randomized Testing of RISC-V CPUs Using Direct Instruction Injection' and of the 2025 RISC-V Summit Europe presentation 'Who tests the TestRIG? Tooling for randomised tandem verification', both of which develop tools for cross-verifying RISC-V implementations, with a particular focus on the CHERI-enabled Toooba processor.

Overview

Franz A. Fuchs is a researcher affiliated with the University of Cambridge (Department of Computer Science and Technology, cl.cam.ac.uk) who works on randomized and mutation-based testing of RISC-V CPUs, with a particular emphasis on the CHERI capability-security extensions. He is listed as a co-author of the journal paper "Randomized Testing of RISC-V CPUs Using Direct Instruction Injection", published in IEEE Design & Test, volume 41, issue 1, pages 40–49, in February 2024 (DOI: 10.1109/MDAT.2023.3262741). The full author list is: Alexandre Joannou, Peter Rugg, Jonathan Woodruff, Franz A. Fuchs, Marno van der Maas, Matthew Naylor, Michael Roe, Robert N. M. Watson, Peter G. Neumann, and Simon W. Moore.

Fuchs is also a co-author of the RISC-V Summit Europe 2025 presentation "Who tests the TestRIG? Tooling for randomised tandem verification" (Peter Rugg, Alexandre Joannou, Jonathan Woodruff, Franz A. Fuchs, Simon W. Moore).

Associated work: TestRIG and Direct Instruction Injection

The 2024 paper describes TestRIG (Testing with Random Instruction Generation), a testing framework for RISC-V implementations. TestRIG cross-verifies implementations against the Sail formal model of the RISC-V architecture by generating random instruction sequences, executing the same sequences on the model and on the implementation under test, and comparing execution traces in tandem execution. The approach does not formally prove equivalence but can demonstrate divergence between an implementation and the model, and is usable at all stages of development.

The paper introduces Direct Instruction Injection (DII) as a test-injection technique. In normal execution the next instruction is fetched from program memory at the address given by the program counter; with DII, the next instruction to be executed is supplied directly by the test harness, regardless of the program counter. TestRIG uses the standard RISC-V Formal Interface (RVFI) to observe state changes after each instruction of the implementation under test.

Findings and methodology

The authors report using TestRIG to test many standard RISC-V extensions and the experimental CHERI security extension. They state that TestRIG was easier to use than instruction-set level unit tests, since individual instructions can be tested as they are implemented without supporting a full testing framework. They also report that random generation gave more thorough test coverage than developer-driven exploration, and that TestRIG was effective at detecting issues not only in instruction semantics but also in the pipeline and data caches. As a result, TestRIG has completely replaced instruction-set level unit testing in the authors' development workflow.

Subsequent work: "Who tests the TestRIG?" (2025)

The 2025 RISC-V Summit Europe presentation, co-authored by Fuchs, discusses improvements to the TestRIG ecosystem since its first public presentation at the RISC-V Summit in Zurich in 2019. The work, which originated at the University of Cambridge, describes:

  • A mutation-based coverage tooling feature. Because the Sail golden model is treated as correct by definition, traditional code coverage can hide bugs in Sail itself. The authors describe auto-generated reports that show the results of mutation-based testing of Sail CHERI functions (e.g., by removing lines of Sail code), indicating whether deletion prevented the model from building, whether a counterexample was successfully detected, or whether no counterexample was detected and additional directed test generation is needed.
  • Features for generating static test suites.
  • A single-implementation mode that enables more traditional fuzzing.

The developments are motivated by testing the Toooba processor, including its CHERI security extensions. TestRIG is in use to test CHERI in the Toooba and CVA6 processors, and the repository has seen community engagement from users and contributors at Microsoft Research, lowRISC, and SCI Semiconductor.

The presentation also describes QuickCheckVEngine, a verification engine that uses Haskell's QuickCheck library to generate tests and automatically shrink any divergences to a minimal reproducer. The RISC-V golden Sail model implements the RVFI-DII interface, allowing implementations to be compared against this executable simulator.

LINKED ENTITIES

1 links
Randomized Testing of RISC-V CPUs using Direct Instruction Injection AUTHORED_BY

CITATIONS

7 sources
7 citations
[1] Franz A. Fuchs is a co-author of the paper 'Randomized Testing of RISC-V CPUs Using Direct Instruction Injection', published in IEEE Design & Test, 41(1):40-49, February 2024 (DOI: 10.1109/MDAT.2023.3262741), with co-authors Alexandre Joannou, Peter Rugg, Jonathan Woodruff, Marno van der Maas, Matthew Naylor, Michael Roe, Robert N. M. Watson, Peter G. Neumann, and Simon W. Moore. Randomized Testing of RISC-V CPUs Using Direct Instruction Injection - researchr publication
[2] Franz A. Fuchs is a co-author of the RISC-V Summit Europe 2025 presentation 'Who tests the TestRIG? Tooling for randomised tandem verification' (Peter Rugg, Alexandre Joannou, Jonathan Woodruff, Franz A. Fuchs, Simon W. Moore, University of Cambridge), which discusses mutation-based coverage tooling, static test suite generation, and a single-implementation fuzzing mode for TestRIG, motivated by testing the Toooba processor with CHERI security extensions. Who tests the TestRIG? Tooling for randomised tandem verification (RISC-V Summit Europe 2025)
[3] TestRIG (Testing with Random Instruction Generation) is a framework that cross-verifies RISC-V implementations against the Sail formal model by generating random instruction sequences, executing them in tandem on the model and the implementation, and comparing execution traces; it does not prove equivalence but can demonstrate divergence, and is usable at all stages of development. Randomized Testing of RISC-V CPUs using Direct Instruction Injection (preprint PDF, CTSRD)
[4] Direct Instruction Injection (DII) is a test-injection technique in which the next instruction to be executed is provided directly by the test harness regardless of the program counter, complementing the RISC-V Formal Interface (RVFI) used to observe per-instruction state changes. Randomized Testing of RISC-V CPUs using Direct Instruction Injection (preprint PDF, CTSRD)
[5] The authors used TestRIG to test many standard RISC-V extensions and the experimental CHERI security extension, and report that it replaced instruction-set level unit testing because it was easier to use, gave more thorough coverage through random generation, and was effective at detecting issues in instruction semantics, the pipeline, and data caches. Randomized Testing of RISC-V CPUs using Direct Instruction Injection (preprint PDF, CTSRD)
[6] The 2025 RISC-V Summit Europe work describes mutation-based coverage tooling for the Sail CHERI golden model, features for generating static test suites, and a single-implementation fuzzing mode, with motivation from testing the Toooba processor including its CHERI extensions, and notes community engagement from Microsoft Research, lowRISC, and SCI Semiconductor. Who tests the TestRIG? Tooling for randomised tandem verification (RISC-V Summit Europe 2025)
[7] TestRIG includes a QuickCheckVEngine verification engine that uses Haskell's QuickCheck library to generate tests and automatically shrink divergences to minimal reproducers, and connects to implementations via the standardized RVFI-DII interface implemented by the Sail golden RISC-V model. Who tests the TestRIG? Tooling for randomised tandem verification (RISC-V Summit Europe 2025)

VERSION HISTORY

v2 · 6/9/2026 · minimax/minimax-m3 (current)
v1 · 5/27/2026 · gpt-5.5