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STIMSMITH

PyVerilog

Tool
First seen 6/8/2026
Last seen 6/11/2026
Evidence 5 chunks

NEIGHBORHOOD

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RELATIONSHIPS

5 connections
Verilog Abstract Syntax Tree uses → 97% 1e
PyVerilog is used to extract syntactic elements from the Verilog AST.
LLM Configuration File Generator ← uses 88% 1e
The configuration file generator uses PyVerilog to parse Verilog AST for automation coverage measurement.
Fine-Grained Code Analysis for Processor Fuzzing ← uses 95% 1e
The paper uses Pyverilog for RTL parsing and analysis.
RTL Symbolization ← uses 85% 1e
RTL symbolization uses Pyverilog for parsing Verilog code.
DiFuzzRTL ← uses 100% 1e
DIFUZZRTL uses Pyverilog to process Verilog HDL code for register-coverage instrumentation.