Robert N. M. Watson
PersonRobert N. M. Watson is listed as a co-author of the 2023 IEEE Design & Test paper "Randomized Testing of RISC-V CPUs using Direct Instruction Injection," which describes TestRIG, a randomized testing framework for RISC-V implementations using tandem execution, RVFI observation, and Direct Instruction Injection.
First seen 5/27/2026
Last seen 6/9/2026
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Overview
Robert N. M. Watson is identified in the provided evidence as one of the authors of the paper "Randomized Testing of RISC-V CPUs using Direct Instruction Injection", published in IEEE Design & Test in 2023. [C1]
Associated technical work
NEIGHBORHOOD
2 nodes · 1 edgesgraph · Robert N. M. Watson · depth=1
RELATIONSHIPS
1 connectionsRobert N. M. Watson is listed as an author of the paper.
CITATIONS
7 sources7 citations — click to expand
[1] Robert N. M. Watson is a co-author of the paper "Randomized Testing of RISC-V CPUs using Direct Instruction Injection," labeled IEEE Design & Test, 2023. Randomized Testing of RISC-V CPUs using Direct
[2] The paper presents TestRIG as a RISC-V testing framework that generates random instruction sequences, executes them on a model and implementation under test, and compares execution traces using tandem execution. Randomized Testing of RISC-V CPUs using Direct
[3] The paper describes the RISC-V Sail model as a human-readable formal model usable for simulation and verification, and states that whole-processor proof automation is not yet routine, motivating TestRIG as a pragmatic divergence-detection approach rather than a proof of equivalence. Randomized Testing of RISC-V CPUs using Direct
[4] Direct Instruction Injection provides the next instruction from the test harness regardless of the CPU program counter, unlike normal program execution where the instruction is fetched from program memory at an address determined by the program counter. Randomized Testing of RISC-V CPUs using Direct
[5] TestRIG uses the RISC-V Formal Interface standard to observe implementation state changes after each instruction. Randomized Testing of RISC-V CPUs using Direct
[6] The paper states that the work compares executable formal models, software ISA simulators, and simulated execution of hardware designs, not completed fabricated chips. Randomized Testing of RISC-V CPUs using Direct
[7] The authors report using TestRIG to test standard RISC-V extensions and the experimental CHERI security extension, and report easier use than unit tests, broader coverage, detection of instruction-semantics, pipeline, and data-cache issues, and replacement of instruction-set-level unit testing for development. Randomized Testing of RISC-V CPUs using Direct