Robert N. M. Watson Wiki

Robert N. M. Watson

Person WIKI v1 · 5/27/2026

Robert N. M. Watson is listed as a co-author of the 2023 IEEE Design & Test paper "Randomized Testing of RISC-V CPUs using Direct Instruction Injection," which describes TestRIG, a randomized testing framework for RISC-V implementations using tandem execution, RVFI observation, and Direct Instruction Injection.

Overview

Robert N. M. Watson is identified in the provided evidence as one of the authors of the paper "Randomized Testing of RISC-V CPUs using Direct Instruction Injection", published in IEEE Design & Test in 2023. [C1]

Associated technical work

The associated paper presents TestRIG — short for Testing with Random Instruction Generation — as a testing framework for RISC-V implementations. The framework is positioned as a pragmatic way to compare an implementation with the RISC-V Sail model by generating random instruction sequences, executing the same sequences on both the model and implementation under test, and comparing execution traces in tandem execution. [C2]

The paper explains that the RISC-V community has standardized a formal model of the architecture in the Sail language, which is described as a human-readable specification that can also be used for simulation and verification. It further notes that full-processor proof automation is not yet routine, motivating TestRIG as a practical equivalence-checking approach that can demonstrate divergence even though it does not prove equivalence. [C3]

Direct Instruction Injection and observation interface

A central technique described in the paper is Direct Instruction Injection (DII). In ordinary execution, a CPU fetches the next instruction from program memory at an address determined by the program counter; with DII, the next instruction is supplied by the test harness regardless of the CPU program counter. [C4]

The paper also states that TestRIG uses the RISC-V Formal Interface (RVFI) standard to observe the change in implementation state after each instruction. [C5]

Testing scope and reported results

The paper clarifies that the work tests executable formal models, software ISA simulators, and simulated execution of hardware designs, rather than completed fabricated chips. [C6]

The authors report using TestRIG to test many standard RISC-V extensions as well as the experimental CHERI security extension. They further report that TestRIG was easier to use than unit tests, provided more thorough test coverage through random generation, detected issues not only in instruction semantics but also in pipelines and data caches, and replaced their instruction-set-level unit testing for development. [C7]

LINKED ENTITIES

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Randomized Testing of RISC-V CPUs using Direct Instruction Injection AUTHORED_BY

CITATIONS

7 sources

7 citations

[1] Robert N. M. Watson is a co-author of the paper "Randomized Testing of RISC-V CPUs using Direct Instruction Injection," labeled IEEE Design & Test, 2023. Randomized Testing of RISC-V CPUs using Direct

[2] The paper presents TestRIG as a RISC-V testing framework that generates random instruction sequences, executes them on a model and implementation under test, and compares execution traces using tandem execution. Randomized Testing of RISC-V CPUs using Direct

[3] The paper describes the RISC-V Sail model as a human-readable formal model usable for simulation and verification, and states that whole-processor proof automation is not yet routine, motivating TestRIG as a pragmatic divergence-detection approach rather than a proof of equivalence. Randomized Testing of RISC-V CPUs using Direct

[4] Direct Instruction Injection provides the next instruction from the test harness regardless of the CPU program counter, unlike normal program execution where the instruction is fetched from program memory at an address determined by the program counter. Randomized Testing of RISC-V CPUs using Direct

[5] TestRIG uses the RISC-V Formal Interface standard to observe implementation state changes after each instruction. Randomized Testing of RISC-V CPUs using Direct

[6] The paper states that the work compares executable formal models, software ISA simulators, and simulated execution of hardware designs, not completed fabricated chips. Randomized Testing of RISC-V CPUs using Direct

[7] The authors report using TestRIG to test standard RISC-V extensions and the experimental CHERI security extension, and report easier use than unit tests, broader coverage, detection of instruction-semantics, pipeline, and data-cache issues, and replacement of instruction-set-level unit testing for development. Randomized Testing of RISC-V CPUs using Direct