2026-06-10
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RISC-V ISA Instruction Set Architecture Processor Verification Reference Model Comparison Co-simulation Direct Instruction Injection RISC-V Formal Interface Formal Verification RTL Simulation Execution Trace Generation Automated Design Inspection LLM-Assisted RTL Code Generation Instruction Fetch Interface Monitoring Register File Write Port Monitoring Fetch and Commit Trace Merging Speculative Fetch Detection Wishbone Bus Interface RTL Wrapper Generation ELF File Execution Read-Modify-Write Memory Operation Custom Benchmark Directed Testing Randomized Instruction Stream Generation Spike ISS Dromajo RISC-V Formal Framework Synopsys ImperasDV Cocotb RTLCoder PyVerilog Fabscalar Yosys AutoSVA Large Language Model Hardware Description Language Verilog Abstract Syntax Tree Jaccard Similarity Coefficient AHB-to-Wishbone Adapter Wishbone-to-Pipelined-Wishbone Adapter Superscalar Processor Verification Program Counter Monitoring Instruction Set Simulator Direct Programming Interface Reorder Buffer Monitoring RV32I Instruction Set Load/Store Byte and Halfword Operations Coverage-Guided Verification FPGA Acceleration for Verification Generic Simulation Testbench LLM Configuration File Generator Benchmarking Large Language Models for Automated Verilog RTL Code Generation RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation Randomized Testing of RISC-V CPUs Using Direct Instruction Injection Efficient Cross-Level Testing for Processor Verification: A RISC-V Case Study StarCoder 2 and the Stack v2: The Next Generation Addressing Verification Challenges of Heterogeneous Systems Based on IBM Power9 Efficient Verification Framework for RISC-V Instruction Extensions with FPGA Acceleration Gabriel Gomes Julio Avelar Gabriel Oliveira Enzo Bertoloti Rodolfo Azevedo Universidade Estadual de Campinas Synopsys IBM RISC-V Foundation The FOSSi Foundation Qwen LLM Family StarCoder2 LLM DeepSeek LLM Family Llama LLM Family Cross-Level Processor Verification Forwarding Structure Testing JALR Instruction Bug Sign Extension Bug First Instruction Fetch Bug RISC-V Foundation
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RISC-V Compliance Testing Mutation Testing Symbolic Execution Instruction Set Architecture Instruction Set Simulation RV32I Coverage-guided Fuzzing Constrained-random Test Generation UVM RTL Functional Coverage Model Checking Compliance Test-suite Virtual Prototype Mutation Classes Specification-based Test Generation Constraint Solving Difference-based Testing Randomized Test Generation angr RISCV-DV riscv-formal OneSpin 360 DV RISC-V Verification App RISC-V Torture Test Generator riscvOVPsim SPIKE GRIFT SAIL RISC-V Model Certitude MicroTESK Mutation-based Compliance Testing for RISC-V Closing the RISC-V Compliance Gap: Looking from the Negative Testing Side Towards Specification and Testing of RISC-V ISA Compliance Verifying Instruction Set Simulators using Coverage-guided Fuzzing Vladimir Herdt Sören Tempel Daniel Große Rolf Drechsler University of Bremen DFKI GmbH Johannes Kepler University Linz Google RISC-V Foundation Synopsys CSR ELF Functional Qualification Bayesian Network Test Generation RISC-V Foundation