Execution Trace

Concept

An execution trace is a structured, time-ordered record of the state observations and state changes produced as a system executes a sequence of operations. In RISC-V processor verification, an execution trace conforming to the RVFI format captures, for each executed instruction, the observed architectural state and the resulting state changes, enabling comparison against a reference (golden) model. More broadly, execution traces underpin program debugging, automated program repair, and the theoretical definition of algorithms as sets of behavioral histories.

First seen 5/29/2026

Last seen 6/10/2026

Evidence 10 chunks

Wiki v1

WIKI

Overview

An execution trace is a structured, time-ordered record of the state observations and state changes that occur as a system executes a sequence of operations. Execution traces are produced by instrumented hardware designs, ISA simulators, formal models, or instrumented software, and they are consumed by verification engines, debuggers, and program-repair systems in order to detect divergence between actual and expected behavior.

Execution Traces in RISC-V Processor Verification

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

1 connections

RVFI Stream part of → 1e

An RVFI Stream carries Execution Traces.

LINKED ENTITIES

1 links

RVFI Stream PART_OF Extracted graph relationship

CITATIONS

8 sources

8 citations — click to expand

[1] Implementations consume a DII instruction trace and generate an RVFI execution trace that details the state observation and state change of each instruction. CTSRD-CHERI/TestRIG

[2] Vengines generate one or more DII streams of instruction traces and consume one or more RVFI streams of execution traces. CTSRD-CHERI/TestRIG

[3] In RVFI-DII the itrace is consumed and the etrace is delivered over the same socket, with implementations bypassing any actual instruction memory and the architectural program counter when in DII mode. CTSRD-CHERI/TestRIG

[4] Generic execution-trace generation combines instruction-fetch fragments and register-file-commit fragments by aligning them in order, since both sequences maintain the same order, and excludes memory write operations. Large-Scale RISC-V Processor Verification Using Automated Design Inspection and a Generic Simulation Method

[5] Speculatively fetched instructions following branches are filtered from the execution trace under a static 'not-taken' prediction, and unexpected commits from canceled instructions are detected as a misaligned trace during comparison. Large-Scale RISC-V Processor Verification Using Automated Design Inspection and a Generic Simulation Method

[6] TestRIG's VEngine injects instruction sequences in RVFI-DII format and consumes RVFI execution traces, and a capable vengine reduces failing traces to minimal counterexamples. Randomized Testing of RISC-V CPUs using Direct Instruction Injection

[7] TraceFixer trains a neural program-repair model on partial execution traces and target correct states to predict source-code edits that eliminate divergence, with top-10 bug-fixing ability improved by 13–20% over an edits-only baseline. TraceFixer: Execution Trace-Driven Program Repair

[8] The notion of an algorithm as a set of execution traces can be reformulated in the general framework of small-step operational semantics, independently of the abstract-state-machine formalism. Execution traces and reduction sequences