RVBS

Tool

RVBS is identified in the TestRIG paper as a reference RISC-V implementation in the TestRIG randomized CPU-testing ecosystem, with a public repository at CTSRD-CHERI/RVBS.

First seen 5/30/2026

Last seen 5/30/2026

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Overview

RVBS is a reference implementation associated with RISC-V CPU testing in the TestRIG ecosystem. The TestRIG paper lists RVBS among RISC-V implementations such as Ibex, Piccolo, Flute, and Toooba, and specifically characterizes RVBS as a reference implementation.

The paper cites the RVBS repository as:

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NEIGHBORHOOD

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RELATIONSHIPS

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TestRIG ← evaluates 90% 1e

TestRIG evaluates RVBS as a reference RISC-V implementation.

RISC-V implements → 90% 1e

RVBS is a RISC-V reference implementation written in Bluespec.

Bluespec uses → 85% 1e

RVBS is written in Bluespec.

LINKED ENTITIES

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TestRIG EVALUATES Extracted graph relationship

RISC-V IMPLEMENTS Extracted graph relationship

Bluespec USES Extracted graph relationship

CITATIONS

3 sources

3 citations — click to collapse

[1] RVBS is listed among RISC-V implementations in the TestRIG paper and is characterized as a reference implementation. Randomized Testing of RISC-V CPUs using Direct

[2] The RVBS repository is cited as https://github.com/CTSRD-CHERI/RVBS. Randomized Testing of RISC-V CPUs using Direct

[3] TestRIG participants require RVFI-DII instrumentation, 8 MiB of memory at 0x80000000, access faults for other addresses, and reset to a known state with zeroed registers and memory. Randomized Testing of RISC-V CPUs using Direct