Overview
RVBS is a reference implementation associated with RISC-V CPU testing in the TestRIG ecosystem. The TestRIG paper lists RVBS among RISC-V implementations such as Ibex, Piccolo, Flute, and Toooba, and specifically characterizes RVBS as a reference implementation.
The paper cites the RVBS repository as:
Role in TestRIG
TestRIG is a randomized testing ecosystem for RISC-V CPUs based on direct instruction injection. In that context, RVBS is one of the implementations considered alongside other RISC-V cores and processors.
The TestRIG ecosystem expects participating implementations to be architecturally equivalent in visible behavior. The paper states that participants require RVFI-DII instrumentation, 8 MiB of memory accessible at address 0x80000000, access faults for other addresses, and support for reset to a known state, including zeroed registers and zeroed memory.