2026-06-11
4 items 187 entities 215 connections
An Approach to Test Programs Generation for Microprocessors Based on Pipeline Hazards Templates
source →Processed 62 entities and 65 relations.
An Approach to Test Programs Generation for Microprocessors Based on Pipeline Hazards Templates Alexander Kamkin Dmitry Vorobyev Institute for System Programming of the Russian Academy of Sciences test program generation pipeline hazards templates ISA formal specification microprocessor verification pipeline hazards cycle-accurate models random test generation model checking based test generation template-based test generation EXPRESSION ADL SMV model checker Operation State Machine Genesys-Pro constraint solving for test generation FSM traversal based test generation test action test situations instruction dependencies combinatorial model-based generation ISA instruction set architecture MIPS ISA data hazards structural hazards control hazards exceptions in pipeline register dependencies address dependencies pipeline interlocks branch prediction simple test actions composite test actions template parameter iterators control logic verification floating point coprocessor CP1 complex arithmetic coprocessor CP2 speculative execution overlapping template composition shift template composition concatenation template composition Specification-Driven Directed Test Generation for Validation of Pipelined Processors P. Mishra N. Dutt Micro-Architecture Coverage Directed Generation of Test Programs S. Ur Y. Yadin Test Program Generation for Microprocessors Test Program Generation for Memory Management Units of Microprocessors fault model test oracle equivalence classes of instructions TLB memory management floating point unit FPU Specification-Driven Directed Test Generation for Validation of Pipelined Processors Micro-Architecture Coverage Directed Generation of Test Programs Test Program Generation for Microprocessors Test Program Generation for Memory Management Units of Microprocessors Genesys-Pro SMV model checker
Processed 46 entities and 53 relations.
CHERI-RISC-V VP++ RISC-V VP++ CHERI RISC-V TestRIG QEMU-CHERI Virtual Prototype RTL random testing RVFI-DII Instruction Set Simulator capability capability compression CHERI Concentrate Compression tagged memory fine-grained memory protection Transaction Level Modeling SystemC virtual memory management Memory Management Unit Direct Instruction Injection Random Instruction Generation CheriBSD Instruction Set Architecture bare-metal software Program Counter Capability Default Data Capability capability sealing Compartment Identifier principle of least privilege software compartmentalization University of Cambridge CHERI Alliance CTSRD Institute for Complex Systems, Johannes Kepler University Linz Andreas Hinterdorfer Daniel Große Manfred Schlägl design space exploration memory corruption bugs CHERI-256 capability format page table walk Translation Lookaside Buffer Load Store Cache Dynamic Base Block Cache RISC-V Formal Interface
Processed 41 entities and 56 relations.
UVM Coverage RISC-V UVM constrained random stimulus generation functional coverage code coverage instruction set architecture RTL Portable Stimulus Standard SystemVerilog coverpoints covergroups cross coverage instruction generation coverage model program level randomization sequence level randomization instruction level randomization hardware-software co-debug verification database RV32I RISCV-DV Spike ISS Synopsys VCS Synopsys Verdi Synopsys VCS Unified Report Generator Synopsys Verdi Hardware Software Debug Solution Synopsys Verdi Coverage Bluespec MCU RTL core MCU testbench RISCV-DV testbench Understanding UVM Coverage for RISC-V Processor Designs Verification Reference Cookbook for Bluespec RISC-V Processors Prabha Krishnaswami Rohit Narkar Amit Goldie Bipul Talukdar Synopsys Bluespec Google University of California, Berkeley RISC-V International
Processed 38 entities and 41 relations.
FuzzWiz Coverage-guided Fuzzing Constrained Random Verification Coverage Directed Test Generation Metamodeling AFL++ Fairfuzz Perffuzz Tortoisefuzz Verilator RFUZZ DIFUZZRTL ProcessorFuzz kcov LLVM JQF Hardware Simulation Binary RTL Mux Toggle Coverage CSR-transition Coverage Control and Status Register Model Driven Architecture MetaFuzz Template of Testbench Template of MetaFuzz Infineon Technologies Google OpenTitan AES KMAC HMAC RISC-V Timer Deepak Narayan Gadde Aman Kumar Djones Lettnin Sebastian Simon Mako Templates FuzzWiz - Fuzzing Framework for Efficient Hardware Coverage