Coverpoints
ConceptCoverpoints are a SystemVerilog construct used for specifying functional coverage, typically within covergroups, and are employed by UVM-based verification environments to reflect the intended functionality of a design.
First seen 6/11/2026
Last seen 6/11/2026
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Coverpoints
Overview
Coverpoints are a language construct provided by SystemVerilog, the hardware description and verification language that also forms the basis for the Universal Verification Methodology (UVM). Together with covergroups and cross coverage, coverpoints form the core set of constructs that SystemVerilog supplies for specifying functional coverage in a verification environment [1].
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2 connectionsSystemVerilog includes coverpoints as a construct for specifying coverage.
UVM Coverage uses coverpoints as defined in SystemVerilog for functional coverage.
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[1] SystemVerilog, the basis for UVM, includes coverpoints, covergroups, and cross coverage as constructs for specifying coverage. Understanding UVM Coverage for RISC-V Processor Designs
[2] UVM's coverage model is implemented by functional coverage that reflects the intended functionality of the design, using coverpoints, covergroups, and cross coverage to provide a faster, scalable approach to verification. Understanding UVM Coverage for RISC-V Processor Designs
[3] Coverpoints are part of the SystemVerilog language itself, separate from but foundational to UVM's coverage methodology. Understanding UVM Coverage for RISC-V Processor Designs