fault model

Concept

In the provided microprocessor-testing case study, a fault model is the class of faults that a testing technique is designed to represent or expose. At circuit level, stuck-at-fault analysis uses mutators to encode fabrication faults such as broken wires. At design-level model-based testing, the implicit fault model can become unclear when generated tests use coarse memory accesses, motivating denser tests or added constraints over generated addresses.

First seen 5/26/2026

Last seen 6/11/2026

Evidence 4 chunks

Wiki v1

WIKI

Overview

A fault model is discussed in the evidence as the fault assumptions incorporated into a testing method. In circuit-oriented testing, the paper describes stuck-at-fault analysis as modifying a circuit design with mutators that capture a fabrication fault model, such as one or more broken wires between gates. This is characterized as a white-box mutation technique because it relies on the structure of the implementation under test. [C1]

Role in test methodology

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

3 connections

stuck-at-fault part of → 90% 1e

Stuck-at-fault is a specific type of fault model used in testing.

An Approach to Test Programs Generation for Microprocessors Based on Pipeline Hazards Templates ← uses 75% 1e

Related work uses fault models; the paper discusses this in context of related approaches.

Specification-Driven Directed Test Generation for Validation of Pipelined Processors ← uses 90% 1e

The Mishra-Dutt approach requires the test developer to define a fault model.

LINKED ENTITIES

1 links

HOL-TestGen can_refine_test_classes_related_to_fault_assumptions The evidence states that HOL-TestGen could generate finer test classes by exploring byte-level or bit-level representations of registers and memory cells.

CITATIONS

5 sources

5 citations — click to expand

[1] Stuck-at-fault analysis uses mutators on a circuit design to capture a fabrication fault model, such as broken wires between gates, and is characterized as a white-box mutation technique. Test Program Generation for a Microprocessor: A Case Study

[2] Stuck-at-fault techniques use circuit structure to build equivalence-class tests that directly incorporate a fault model, are effective for medium-size circuits, but may miss design flaws such as memory byte-alignment write-read errors. Test Program Generation for a Microprocessor: A Case Study

[3] Constraint solving and random instantiation can generate test sequences with coarsely grained memory access, making the underlying fault model arcane and associated with distant-memory interferences; denser testing is recommended for such faults. Test Program Generation for a Microprocessor: A Case Study

[4] Additional constraints can reduce the uniformity domain by bounding address ranges or constraining loads to addresses written by stores, and can improve coverage by dividing the domain into interesting sub-domains. Test Program Generation for a Microprocessor: A Case Study

[5] The VAMP study stayed at the design level despite having a gate-level model, and test equivalence classes could be refined by using HOL-TestGen to explore byte-level or bit-level representations of registers and memory cells. Test Program Generation for a Microprocessor: A Case Study