Hardware-Software Co-Debug

Concept

Hardware-software co-debug is a verification methodology that combines RTL-level hardware debug with embedded software (C/assembly) debug in a single, time-synchronized environment. It allows engineers to view C/assembly code, C variables, and the stack alongside the executing RTL, with hardware and software cursors aligned to the same simulation time. The approach is used to verify processor and SoC designs—particularly when constrained-random stimulus makes software-side visibility otherwise low—and supports simultaneous debugging of multiple cores in an SoC.

First seen 6/11/2026

Last seen 6/11/2026

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Hardware-Software Co-Debug

Overview

Hardware-software co-debug (also written as HW/SW co-debug or hardware/software co-debug) is a debug methodology that integrates two traditionally separate views into a single, time-synchronized environment:

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Synopsys Verdi Hardware Software Debug Solution ← implements 100% 1e

The Synopsys Verdi HW/SW Debug Solution implements hardware-software co-debug capability.

Synopsys Verdi ← uses 95% 1e

Synopsys Verdi combined with HW/SW Debug Solution enables hardware-software co-debug.

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CITATIONS

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[1] The Synopsys Verdi Automated Debug System, combined with the Synopsys Verdi Hardware Software Debug (HW/SW Debug) Solution, provides a method for debugging embedded software. [PDF] Understanding UVM Coverage for RISC-V Processor Designs

[2] The approach integrates debug of the RTL core design at the hardware level and debug of the embedded code at the assembly or C level. [PDF] Understanding UVM Coverage for RISC-V Processor Designs

[3] C/assembly code, C variables, and the stack are visible, with the hardware and software debugging synchronized in time. [PDF] Understanding UVM Coverage for RISC-V Processor Designs

[4] Multiple cores in an SoC design can be debugged simultaneously. [PDF] Understanding UVM Coverage for RISC-V Processor Designs

[5] The co-debug solution proved useful during the Bluespec MCU verification by providing more visibility into the generated RISC-V instructions. [PDF] Understanding UVM Coverage for RISC-V Processor Designs

[6] The solution was especially helpful while debugging constrained random sequences, where user visibility into the software side may be limited. [PDF] Understanding UVM Coverage for RISC-V Processor Designs

[7] Figure 7 of the white paper shows the MCU RTL design and the executing RISC-V code opened in the Synopsys Verdi HW-SW Debug GUI, with cursor locations demonstrating that simulation time is synchronized between the hardware and software views. [PDF] Understanding UVM Coverage for RISC-V Processor Designs