Address Dependencies
ConceptAddress dependencies are a class of instruction dependencies in microprocessor pipelining that arise from the internal organization of memory management units, capturing relationships between instructions based on virtual addresses, TLB entries, physical addresses, and cache rows.
First seen 6/11/2026
Last seen 6/11/2026
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Address Dependencies
Definition
Address dependencies are a type of instruction dependency in microprocessor pipelining. They have a more complex structure than register dependencies and are tied to the internal organization of memory management units. They describe how two instructions relate to each other through the memory subsystem rather than through explicit register operands.
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2 connections An Approach to Test Programs Generation for Microprocessors Based on Pipeline Hazards Templates ← uses 90% 1e
The paper uses address dependencies as a type of instruction dependency related to memory management.
Address dependencies are a type of instruction dependency.
CITATIONS
4 sources4 citations — click to collapse
[1] Address dependencies have a more complex structure than register dependencies and are related to the internal organization of memory management units. An Approach to Test Programs Generation for Microprocessors Based on Pipeline Hazards Templates
[2] The examples of address dependencies are VAEqual (equality of virtual addresses), TLBEqual (equality of TLB entries), PAEqual (equality of physical addresses), and CacheRowEqual (equality of cache rows). An Approach to Test Programs Generation for Microprocessors Based on Pipeline Hazards Templates
[3] Register dependencies are expressed as equality of registers used as operands of two instructions and are classified as read-read, read-write, write-read, and write-write. An Approach to Test Programs Generation for Microprocessors Based on Pipeline Hazards Templates
[4] In a pipeline hazard template, a hazard situation is specified by constraints on parameters P1 through PK, and dependencies partition the specification into equivalence classes that form the basis for constructing iterators for test program generation. An Approach to Test Programs Generation for Microprocessors Based on Pipeline Hazards Templates