AES (Advanced Encryption Standard)

Concept

AES is a widely adopted symmetric block cipher used to secure embedded systems, IoT platforms, and general-purpose computing. It is implemented both as a software algorithm and as a hardware IP core, notably within the OpenTitan open-source root-of-trust project, and has been the target of hardware-accelerator research (e.g., AES-RV) and of hardware verification via the FuzzWiz fuzzing framework. Variants augmenting AES key scheduling with chaotic maps have also been proposed to strengthen key confidentiality at a modest computational cost.

First seen 6/11/2026

Last seen 6/11/2026

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AES (Advanced Encryption Standard)

Overview

The Advanced Encryption Standard (AES) is a widely adopted cryptographic algorithm that is essential for securing embedded systems and Internet of Things (IoT) platforms [arxiv:2505.11880v1]. It is a symmetric block cipher that operates on multiple block sizes and supports several standardized key sizes, and is generally considered a secure algorithm, although some residual security concerns are associated with its S-Box and key handling [arxiv:1307.3057v1].

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RELATIONSHIPS

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FuzzWiz ← evaluates 100% 1e

FuzzWiz is evaluated on the AES IP core from OpenTitan.

OpenTitan part of → 100% 1e

OpenTitan includes AES as one of its IP cores.

LINKED ENTITIES

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FuzzWiz EVALUATES Extracted graph relationship

OpenTitan PART_OF Extracted graph relationship

CITATIONS

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5 citations — click to expand

[1] AES is a widely adopted cryptographic algorithm essential for securing embedded systems and IoT platforms, and existing AES hardware accelerators often face trade-offs in performance, energy efficiency, and flexibility. AES-RV: Hardware-Efficient RISC-V Accelerator with Low-Latency AES Instruction Extension for IoT Security

[2] AES-RV integrates high-bandwidth internal buffers, a specialized AES unit with custom low-latency instructions, and a pipelined system with ping-pong memory transfer, and on a Xilinx ZCU102 SoC FPGA achieves up to 255.97× speedup and up to 453.04× higher energy efficiency versus baseline CPU/GPU platforms. AES-RV: Hardware-Efficient RISC-V Accelerator with Low-Latency AES Instruction Extension for IoT Security

[3] AES is one of the IP cores in Google's OpenTitan project and is crucial for data encryption, offering high-level security for various block sizes; it was selected as a Design Under Verification alongside KMAC, HMAC, and RV-Timer. FuzzWiz - Fuzzing Framework for Efficient Hardware Coverage

[4] In the FuzzWiz evaluation, the AFL++ fuzzer was predominant for the AES and KMAC designs, reaching better coverage than Fairfuzz within 10 hours; AFL++ attained coverage faster than other engines, while Perffuzz and Tortoisefuzz achieved comparatively lower coverage on the majority of designs. FuzzWiz - Fuzzing Framework for Efficient Hardware Coverage

[5] AES is considered a secured algorithm, but some security issues remain in the S-Box and the key; modified AES variants that use 1-D logistic chaos, cross chaos, or combinations thereof strengthen key protection at the cost of higher CPU time. Chaotic Variations of AES Algorithm