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AES (Advanced Encryption Standard)

Concept WIKI v1 · 6/11/2026

AES is a widely adopted symmetric block cipher used to secure embedded systems, IoT platforms, and general-purpose computing. It is implemented both as a software algorithm and as a hardware IP core, notably within the OpenTitan open-source root-of-trust project, and has been the target of hardware-accelerator research (e.g., AES-RV) and of hardware verification via the FuzzWiz fuzzing framework. Variants augmenting AES key scheduling with chaotic maps have also been proposed to strengthen key confidentiality at a modest computational cost.

AES (Advanced Encryption Standard)

Overview

The Advanced Encryption Standard (AES) is a widely adopted cryptographic algorithm that is essential for securing embedded systems and Internet of Things (IoT) platforms [arxiv:2505.11880v1]. It is a symmetric block cipher that operates on multiple block sizes and supports several standardized key sizes, and is generally considered a secure algorithm, although some residual security concerns are associated with its S-Box and key handling [arxiv:1307.3057v1].

Hardware acceleration for embedded and IoT use

Existing AES hardware accelerators are often constrained by trade-offs among performance, energy efficiency, and flexibility [arxiv:2505.11880v1]. To address these constraints, AES-RV was proposed as a hardware-efficient RISC-V accelerator that adds low-latency AES instruction extensions optimized for real-time processing across all AES modes and key sizes.

AES-RV integrates three core innovations:

  • High-bandwidth internal buffers that enable continuous data processing.
  • A specialized AES unit that exposes custom low-latency instructions to the RISC-V pipeline.
  • A pipelined system backed by a ping-pong memory transfer mechanism that overlaps data movement with computation.

The design was implemented on a Xilinx ZCU102 SoC FPGA and, in the reported evaluation, achieved up to 255.97× speedup and up to 453.04× higher energy efficiency relative to baseline and conventional CPU/GPU platforms, with superior throughput and area efficiency against state-of-the-art AES accelerators [arxiv:2505.11880v1].

AES as an OpenTitan IP core

AES appears as one of the principal cryptographic Intellectual Property (IP) cores in Google's OpenTitan open-source silicon root-of-trust project [arxiv:2410.17732v1]. In the OpenTitan design, the AES core is responsible for data encryption and is described as offering high-level security for various block sizes. Together with the KMAC, HMAC, and RV-Timer cores, AES was selected as a Design Under Verification (DUV) in the FuzzWiz study because cryptographic and system-control blocks are fundamental to security and historically require long simulation campaigns to reach coverage closure.

Hardware verification with FuzzWiz

FuzzWiz, a fuzzing framework for efficient hardware coverage, was applied to the OpenTitan AES core alongside KMAC, HMAC, and RV-Timer. In the 10-hour fuzzing experiments reported in the FuzzWiz paper, the AFL++ fuzzer engine was predominant for the AES and KMAC designs, reaching better coverage than Fairfuzz within the same time budget. AFL++ was observed to attain coverage faster than the other engines evaluated, attributed to its superior instrumentation and integration into a Linux kernel module, while Perffuzz and Tortoisefuzz achieved comparatively lower coverage on the majority of the designs [arxiv:2410.17732v1].

Key-schedule hardening with chaotic variations

To strengthen AES against key-related attacks, modified variants have been proposed that augment the AES key schedule with chaotic map variations, including a 1-D logistic chaos equation, a cross chaos equation, and combinations of both [arxiv:1307.3057v1]. These variants trade increased CPU time for additional protection of the key, and the authors report that the modified algorithms remain practical while offering greater resistance to unauthorized recovery of the secret key, making them candidates for highly sensitive information [arxiv:1307.3057v1].

Related entities

  • FuzzWiz — A hardware-fuzzing framework that evaluates the OpenTitan AES IP core and compares fuzzing engines on it (relation: evaluated by).
  • OpenTitan — The open-source root-of-trust project in which the AES IP core is included alongside KMAC, HMAC, and RV-Timer (relation: part of).

LINKED ENTITIES

2 links
FuzzWiz EVALUATES
OpenTitan PART_OF

CITATIONS

5 sources
5 citations
[1] AES is a widely adopted cryptographic algorithm essential for securing embedded systems and IoT platforms, and existing AES hardware accelerators often face trade-offs in performance, energy efficiency, and flexibility. AES-RV: Hardware-Efficient RISC-V Accelerator with Low-Latency AES Instruction Extension for IoT Security
[2] AES-RV integrates high-bandwidth internal buffers, a specialized AES unit with custom low-latency instructions, and a pipelined system with ping-pong memory transfer, and on a Xilinx ZCU102 SoC FPGA achieves up to 255.97× speedup and up to 453.04× higher energy efficiency versus baseline CPU/GPU platforms. AES-RV: Hardware-Efficient RISC-V Accelerator with Low-Latency AES Instruction Extension for IoT Security
[3] AES is one of the IP cores in Google's OpenTitan project and is crucial for data encryption, offering high-level security for various block sizes; it was selected as a Design Under Verification alongside KMAC, HMAC, and RV-Timer. FuzzWiz - Fuzzing Framework for Efficient Hardware Coverage
[4] In the FuzzWiz evaluation, the AFL++ fuzzer was predominant for the AES and KMAC designs, reaching better coverage than Fairfuzz within 10 hours; AFL++ attained coverage faster than other engines, while Perffuzz and Tortoisefuzz achieved comparatively lower coverage on the majority of designs. FuzzWiz - Fuzzing Framework for Efficient Hardware Coverage
[5] AES is considered a secured algorithm, but some security issues remain in the S-Box and the key; modified AES variants that use 1-D logistic chaos, cross chaos, or combinations thereof strengthen key protection at the cost of higher CPU time. Chaotic Variations of AES Algorithm