instruction set simulation

Concept

Instruction set simulation, in the provided evidence, is the use of software that models how a processor or accelerator should behave for given instructions. In a RISC-V vector accelerator verification environment, the Spike RISC-V ISA simulator was used as a reference model for step-by-step co-simulation and result checking.

First seen 5/28/2026

Last seen 5/28/2026

Evidence 2 chunks

Wiki v1

WIKI

Overview

Instruction set simulation is represented in the evidence by the use of an ISA simulator as a software reference model during hardware verification. The reference model predicts how the design should behave from its inputs, accepts instructions as input, and generates expected results for comparison with the hardware design under verification.

Use in verification

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RELATIONSHIPS

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spike ← implements 98% 1e

Spike is a RISC-V ISA simulator used for instruction set simulation.

LINKED ENTITIES

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spike IMPLEMENTS Extracted graph relationship

CITATIONS

4 sources

4 citations — click to collapse

[1] A reference model in the cited verification environment predicted how the design should behave, accepted instructions as input, and generated expected results. Functional Verification of a RISC-V Vector Accelerator

[2] Spike was used as the RISC-V ISA simulator for co-simulation in a UVM verification environment. Functional Verification of a RISC-V Vector Accelerator

[3] The RISC-V vector accelerator verification infrastructure performed step-by-step co-simulation of vector instructions using Spike as an instruction set simulator reference model. Functional Verification of a RISC-V Vector Accelerator

[4] Each completed vector instruction was compared against the reference model during co-simulation of constrained-random binaries and C programs. Functional Verification of a RISC-V Vector Accelerator