Peter G. Neumann

Person

Peter G. Neumann is listed as a co-author of the paper "Randomized Testing of RISC-V CPUs using Direct Instruction Injection," an IEEE Design & Test 2023 article about TestRIG, a randomized testing framework for RISC-V implementations.

First seen 5/27/2026

Last seen 6/9/2026

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Overview

Peter G. Neumann is identified in the available evidence as one of the authors of the paper "Randomized Testing of RISC-V CPUs using Direct Instruction Injection". The paper appears in IEEE Design & Test, 2023 and presents TestRIG, a testing framework for RISC-V implementations based on randomized instruction generation and Direct Instruction Injection (DII). [Author listing; TestRIG paper context]

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Randomized Testing of RISC-V CPUs using Direct Instruction Injection ← authored by 100% 6e

Peter G. Neumann is listed as an author of the paper.

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[1] Peter G. Neumann is listed as a co-author of "Randomized Testing of RISC-V CPUs using Direct Instruction Injection." Randomized Testing of RISC-V CPUs using Direct

[2] The paper appears as an IEEE Design & Test 2023 article and describes TestRIG as a testing framework for RISC-V implementations. Randomized Testing of RISC-V CPUs using Direct

[3] TestRIG generates random instruction sequences, runs them on both a model and an implementation under test, and compares execution traces in tandem execution. Randomized Testing of RISC-V CPUs using Direct

[4] Direct Instruction Injection supplies the next instruction from the test harness regardless of the CPU program counter. Randomized Testing of RISC-V CPUs using Direct

[5] The paper discusses RISC-V formal modeling in Sail and frames TestRIG as a pragmatic compromise because full-processor formal equivalence proof is not yet routinely automated. Randomized Testing of RISC-V CPUs using Direct

[6] The authors report using TestRIG to test standard RISC-V extensions and the experimental CHERI security extension, and state that it replaced their instruction-set-level unit testing for development. Randomized Testing of RISC-V CPUs using Direct