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Peter G. Neumann

Person WIKI v1 · 5/27/2026

Peter G. Neumann is listed as a co-author of the paper "Randomized Testing of RISC-V CPUs using Direct Instruction Injection," an IEEE Design & Test 2023 article about TestRIG, a randomized testing framework for RISC-V implementations.

Overview

Peter G. Neumann is identified in the available evidence as one of the authors of the paper "Randomized Testing of RISC-V CPUs using Direct Instruction Injection". The paper appears in IEEE Design & Test, 2023 and presents TestRIG, a testing framework for RISC-V implementations based on randomized instruction generation and Direct Instruction Injection (DII). [Author listing; TestRIG paper context]

Associated work

Randomized Testing of RISC-V CPUs using Direct Instruction Injection

The paper lists the following authors: Alexandre Joannou, Peter Rugg, Jonathan Woodruff, Franz A. Fuchs, Marno van der Maas, Matthew Naylor, Michael Roe, Robert N. M. Watson, Peter G. Neumann, and Simon W. Moore. [Author listing]

The work describes TestRIG, short for Testing with Random Instruction Generation, as a framework for testing RISC-V implementations. It compares executable formal models, software ISA simulators, and simulated execution of hardware designs by generating random instruction sequences, executing them on both a model and an implementation under test, and comparing execution traces. [TestRIG framework]

The paper also describes Direct Instruction Injection (DII), a technique in which the next instruction to be executed is supplied by the test harness regardless of the CPU program counter, rather than being fetched normally from program memory. [Direct Instruction Injection]

Research context in the cited paper

The cited paper situates TestRIG in the context of RISC-V formal modeling using the Sail language. It notes that while full-processor formal equivalence proof remains difficult, randomized tandem execution can reveal divergences between a formal model and an implementation during development. [RISC-V and Sail context]

The authors report using TestRIG to test many standard RISC-V extensions and the experimental CHERI security extension. They also state that TestRIG became easier to use than instruction-set-level unit tests in their development workflow and provided more thorough coverage through randomized generation. [TestRIG evaluation]

LINKED ENTITIES

1 links
Randomized Testing of RISC-V CPUs using Direct Instruction Injection AUTHORED_BY

CITATIONS

6 sources
6 citations
[1] Peter G. Neumann is listed as a co-author of "Randomized Testing of RISC-V CPUs using Direct Instruction Injection." Randomized Testing of RISC-V CPUs using Direct
[2] The paper appears as an IEEE Design & Test 2023 article and describes TestRIG as a testing framework for RISC-V implementations. Randomized Testing of RISC-V CPUs using Direct
[3] TestRIG generates random instruction sequences, runs them on both a model and an implementation under test, and compares execution traces in tandem execution. Randomized Testing of RISC-V CPUs using Direct
[4] Direct Instruction Injection supplies the next instruction from the test harness regardless of the CPU program counter. Randomized Testing of RISC-V CPUs using Direct
[5] The paper discusses RISC-V formal modeling in Sail and frames TestRIG as a pragmatic compromise because full-processor formal equivalence proof is not yet routinely automated. Randomized Testing of RISC-V CPUs using Direct
[6] The authors report using TestRIG to test standard RISC-V extensions and the experimental CHERI security extension, and state that it replaced their instruction-set-level unit testing for development. Randomized Testing of RISC-V CPUs using Direct