Concept
Concept
4932 entities#
1 RISC-V
578 2 RTL
239 3 RISC-V ISA
177 4 Functional Coverage
165 5 Instruction Set Architecture
141 6 formal verification
121 7 UVM
103 8 Instruction Set Simulator
97 9 Co-simulation
88 10 Functional Verification
86 11 RTL Simulation
85 12 SystemVerilog
81 13 Design Under Test
79 14 Coverage-guided Fuzzing
78 15 Golden Reference Model
77 16 Code Coverage
76 17 Hardware fuzzing
74 18 Instruction Set Architecture (ISA)
73 19 Stimulus Generation
67 20 Instruction Set Simulator (ISS)
66 21 Reference Model
60 22 CPU
54 23 Register-Transfer Level
54 24 simulation-based verification
53 25 CHERI
52 26 Control and Status Registers
51 27 test program generation
51 28 Design Under Test (DUT)
49 29 Constrained Random Verification
43 30 Register File
42 31 Processor Verification
42 32 Finite State Machine
41 33 Large Language Model
40 34 Random Instruction Generation
39 35 Testbench
38 36 Constraint Satisfaction Problem
38 37 Test Template
37 38 Instruction Stream Generation
35 39 Control and Status Registers (CSRs)
35 40 out-of-order execution
34 41 pre-silicon verification
33 42 BOOM
33 43 device under test
32 44 RISC-V Vector extension
31 45 Microprocessor Verification
31 46 ISA Simulation
31 47 seed corpus
30 48 Hardware Description Language
30 49 Verification Plan
30 50 Register-Transfer Level (RTL)
30 51 Instruction Sequence Generation
30 52 Verilog
29 53 Coverage Closure
28 54 Symbolic Execution
28 55 Virtual Prototype
27 56 FPGA
27 57 mutation testing
27 58 coverage metrics
27 59 Branch Coverage
27 60 CVA6
27 61 Testcase Generation
27 62 pipeline
26 63 RV32I
26 64 Branch Prediction
26 65 Architectural State
25 66 speculative execution
25 67 Basic Block
25 68 Rocket
25 69 ARM instruction set architecture
24 70 Transaction Level Modeling
24 71 CVA6
24 72 Architecture Description Language
23 73 RTL verification
23 74 Physical Memory Protection
23 75 constrained-random test generation
23 76 Differential Testing
23 77 RVFI-DII
23 78 Coverage-Driven Verification
22 79 ARM Architecture
22 80 Model Checking
22 81 ISA Simulator
22 82 Instruction Scenario
22 83 Regression Testing
22 84 CSR
22 85 constraint solving
22 86 x86 Architecture
22 87 System-on-Chip (SoC)
21 88 design verification
21 89 design space exploration
21 90 Design Under Verification
21 91 microarchitectural state
21 92 Coverpoint
21 93 toggle coverage
20 94 Instruction Decoder
20 95 FSM coverage
20 96 control flow graph
20 97 coverage metric
20 98 Processor Fuzzing
20 99 RISC-V Instruction Set Architecture
19 100 BOOM
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