2026-07-12
6 items 266 entities 334 connections
Processed 66 entities and 73 relations.
Fuzzing Coverage-based Greybox Fuzzing Greybox Fuzzing Whitebox Fuzzing Blackbox Fuzzing Mutation-based Fuzzing Generation-based Fuzzing Snapshot-based Fuzzing Multi-target Coverage-based Greybox Fuzzing Code Coverage Measurement Symbolic Execution Basic Block Coverage Tracing TCG-based Instrumentation Address-based Coverage Filtering VM Snapshot Save and Restore Power Scheduling Binary Search for Address Filtering MTCFuzz QEMU AFL++ libFuzzer syzkaller ItyFuzz KCOV Ghidra addr2line bpftrace GCC LLVM Code Coverage Basic Block Seed Corpus Tiny Code Generator QMP Protocol ELF Binary Format Shared Memory Coverage Map TrustZone Trusted Execution Environment Memory Address Isolation IsInteresting Function AssignEnergy Function Test Harness qcow2 Snapshot Storage Sanitizer Coverage Instrumentation Vulnerability Discovery CVE-2025-40031 OpenSBI OP-TEE RISC-V Architecture ARM Architecture Linux Kernel Firmware Trusted Firmware-A Multi-target Coverage Feedback Coverage Visualization Fuzzing Workflow Masami Ichikawa Kuniyasu Suzaki Institute of Information Security Multi-target Coverage-based Greybox Fuzzing (Master's Thesis 2025) mtcfuzz_record_tb_exec analyze_coverage mtcfuzz-trace-start QMP command mtcfuzz-trace-stop QMP command afl-fuzz.c save_if_interesting afl-fuzz.c has_new_bits
Processed 37 entities and 49 relations.
COMS30026 Design Verification: Stimuli Generation Kerstin Eder Avi Ziv IBM Research Labs Haifa University of Bristol Stimuli Generation Verification Plan Test Scenarios Matrix PowerPC Processor RISC Architecture Pipeline Forwarding Mechanism Instruction Pair Coverage Distributed Generators Single Unified Generator Synchronized Generators Level of Abstraction Bit-Level Abstraction Sequence-Level Abstraction Command and Data Instruction Level Algorithmic Level Abstraction Error Injection Offline Test Generation Online Test Generation Out-of-Order Instruction Generation Static Test Generation Dynamic Test Generation Reference Model Test Length Constrained Pseudo-Random Stimulus Generation Corner Case Coverage Design Under Verification Dispatch Queue Instruction Fetch Instruction Cache Data Cache Processor Verification Environment
Processed 39 entities and 46 relations.
Integrated Circuit Verification Universal Verification Methodology HAVEN Large Language Model Hardware Description Language SystemVerilog UVM Testbench UVM Sequence Protocol-Aware Sequence Domain-Specific Language Jinja2 Template Engine Rule-Based Code Generation UVM Blueprint Protocol Flows Bus Functional Model Coverage Gap Report Device Under Test AXI4-Lite Protocol Wishbone Protocol Direct Interface Protocol Bus-Handshake Timing Functional Coverage Code Coverage Constrained Random Stimulus LLM Agent AutoBench CorrectBench ConfiBench UVM2 RTL UVM Driver UVM Monitor UVM Scoreboard Structured JSON Artifact Field Value Sweep Toggle Pattern FIFO Stress Test Register Write Step Poll Step Compile-Fix Loop
Processed 37 entities and 50 relations.
Symbolic Execution KLEE Co-Simulation Instruction Set Simulator (ISS) RTL RISC-V MicroRV32 RISC-V VP Verilator Fuzzing Constrained Random Instruction Generation Model-Based Test Generation Symbolic Instruction Memory Symbolic Data Memory Sliced Symbolic Registers Symbolic Execution Interface Voter (Mismatch Detection) RISC-V Formal Interface (RVFI) riscv-formal Bounded Model Checking (BMC) Instruction Stream SpinalHDL LLVM Coverage-Guided Fuzzing Control and Status Registers (CSRs) Error Injection VexRiscV PicoRV32 RISCV-DV Niklas Bruns Vladimir Herdt Rolf Drechsler University of Bremen DFKI GmbH Processor Verification using Symbolic Execution: A RISC-V Case-Study Processor Verification Instruction Set Architecture (ISA)
Processed 28 entities and 25 relations.
stimulus generation pseudo-random test-program generation RISCV-DV COREV-DV manually generated C and Assembly programs Coremark Embench IOT test suite bus cycle delay randomization UVM Agent Open Bus step&compare ImperasDV reference model instruction set simulator Core-V-Verif RISC-V Verification Interface Universal Verification Methodology Formal Verification Siemens EDA Onespin RISC-V ISA app CV32E40P RV32Xpulp ISA extension OpenHW Group Dolphin Design Google Imperas Software Embecosm CV32E40P updates: customizing an open-source RISC-V core at industrial-grade
Processed 59 entities and 91 relations.
TaPaFuzz Fuzz Testing Graybox Fuzzing Control Flow Coverage Coverage Map Basic Block Coverage Control Flow Edge Coverage Corpus Input Mutation Blackbox Fuzzing Whitebox Fuzzing FPGA Hardware Acceleration ISA Emulation AXI Bus Protocol Fuzzer Result Aggregation Cache Invalidation Branch Predictor Persistent Mode Forkserver Hash-Based Indexing Processing Element Partial Design Reset Dynamic Binary Translation Compiler Instrumentation Hardware-Based Control Flow Tracing AFL++ LibAFL LibFuzzer QEMU TaPaSCo Xilinx Vivado CVA5 RISC-V Core AXI Reset Wrapper Fuzzer Result Aggregation Hardware libtapasco ArduinoJson RISC-V ISA IoT Firmware Soft-Core Processor Scratchpad Memory Memory-Mapped IO PCIe Interface Florian Meisel David Volz Christoph Spang Dat Tran Andreas Koch Andrea Fioraldi Dominik Maier Michal Zalewski Technical University of Darmstadt Embedded Systems and Applications Group TaPaFuzz: An FPGA-Accelerated Framework for RISC-V IoT Graybox Fuzzing AFL++: Combining Incremental Steps of Fuzzing Research The TaPaSCo Open-Source Toolflow DDR4 Memory Interrupt Request System-on-Chip Hardware-Based Control Flow Tracing