2026-07-11
6 items 219 entities 222 connections
Processed 36 entities and 39 relations.
HWFuzz RISC-V processor verification fuzzing coverage-directed generation RISC-V instruction sequence generation FPGA acceleration hardware fuzzer IP mutation-based fuzzing random instruction generation stimuli packing stimuli constraints instruction injector coverage corpus synthesizable coverpoints differential checking ENCORE Rocket Core design-under-test (DUT) RTL design RFUZZ DifuzzRTL TheHuzz Cascade American Fuzzy Lop (AFL) libfuzzer RV64I extension RV64G extension Zynq UltraScale+ Yang Zhong Haoran Wu Yungang Bao Kan Shi Institute of Computing Technology, Chinese Academy of Sciences University of Chinese Academy of Sciences University of Cambridge HWFuzz: An FPGA-Accelerated Fuzzing Framework for Efficient RISC-V Verification
Processed 65 entities and 71 relations.
ZP Cosim Zynq-Parrot Dromajo Surelog Universal Hardware Data Model Verilator Synopsys VCS Synopsys Zebu Server 5 Cadence Palladium Z1/Z2 AFL++ FuzzFactory Synopsys VC Formal RISC-V Proxy Kernel RISCV-DV BaseJump STL Chisel TL-Verilog Bluespec FPGA-accelerated cosimulation automated coverage instrumentation Mux Toggle Coverage coverage metric hardware fuzzing cosimulation golden reference model program generator test vector mutation coverpoint unreachability analysis coverage aliasing localized cross products structural coverage functional coverage formal verification case-statement coverage toggle-only coverage coverspace preprocessing hardware state-space ISA-level coverage microarchitectural coverage FSM coverage agile chip design randomized test vectors FPGA emulation FPGA shell SAT solver Reinforcement Learning for hardware fuzzing RISC-V processor verification BlackParrot Ultra96v2 Coverage Walker VPI API SystemVerilog RTL simulation Anoop Mysore Nataraja Michael Taylor University of Washington Bespoke Silicon Group Air Force Research Laboratory DARPA SPEC 2017 benchmarks BEEBS benchmarks RISC-V Tests Zynq Farm AXI interface
Processed 39 entities and 25 relations.
SV/UVM Testbench Dynamic Simulation Formal Property Verification (FPV) SVA Testbench TileLink Protocol Compliance Verification PWRMGR IP CIP Testbench Architecture pwrmgr_env_pkg tb.sv pwrmgr.sv tl_agent ralgen regtool RAL Model pwrmgr_base_vseq pwrmgr_smoke_vseq pwrmgr_wakeup_vseq pwrmgr_aborted_low_power_vseq pwrmgr_reset_vseq pwrmgr_wakeup_reset_vseq pwrmgr_lowpower_wakeup_race_vseq Functional Coverage Model Constrained Random Stimulus Slow Responder Task Fast Responder Task Clock Domain Crossing (CDC) Slow FSM Fast FSM pwrmgr_clock_enables_sva_if pwrmgr_ast_sva_if Low Power Entry/Exit Wakeup Sources Reset Request Handling pwrmgr_bind.sv tlul_assert clkmgr_pwrmgr_sva_if dvsim lowRISC OpenTitan
Processed 27 entities and 29 relations.
Difftest Co-Simulation NEMU Spike Verilator VCS Fork-Based Fast Checkpointing LightSSS Profile-Guided Optimization Design Under Test Golden Reference Model Architectural State RISC-V RTL XiangShan scripts/xiangshan.py SimTop.sv difftest-interface.sv NUMA-Aware Core Allocation Cache Coherence SPEC CPU 2006 CoreMark RV64GCBV numactl Multi-Core Validation XSNoCDiffTopConfig Multi-Core Validation
Processed 40 entities and 57 relations.
Towards a framework for constraint-based test case generation François Degrave Tom Schrijvers Wim Vanhoof Katholieke Universiteit Leuven University of Namur constraint-based test case generation constraint programming symbolic execution whitebox testing structural coverage CP search strategies depth-bounded search branch-and-bound optimization random test data generation constraint propagation Constraint Handling Rules MC/DC coverage execution path control-flow graph heap-allocated data structures pointer-based data structures cons cell cyclic data structures coverage criterion regression testing test suite non-determinism in constraint solving Herbrand equality program state constraint variable ImpL imperative language SWI-Prolog prototype Graphviz ATGen Monadic Constraint Programming framework Automatic generation of test inputs for Mercury Monadic Constraint Programming Mercury logic programming language Spark ADA