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Case-statement coverage

Concept

Case-statement coverage is a structural/code coverage metric used in hardware verification to assess how completely a test vector exercises all case-statement control paths. It is implemented as a proof-of-concept within the ZP Cosim tool and is positioned as a supplementary perspective on verification progress rather than a standalone metric.

First seen 7/11/2026
Last seen 7/11/2026
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Overview

Case-statement coverage is a structural/code coverage metric used in hardware verification. It assesses the completeness of a test vector in exercising all the case-statement control paths in a hardware design [1]. The metric provides visibility into whether a given testbench has driven the design under test (DUT) through every branch of its case statements.

Role in Verification

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RELATIONSHIPS

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ZP Cosim ← implements 90% 1e
ZP Cosim provides a proof-of-concept case-statement coverage implementation

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CITATIONS

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[1] Case-statement coverage is a structural/code coverage metric that assesses the completeness of a test vector in exercising all the case statement control paths. ©Copyright 2023 Anoop Mysore Nataraja (ZP Cosim thesis)
[2] Case-statement coverage is not a standalone metric; it provides another perspective on one frontier of verification progress. ©Copyright 2023 Anoop Mysore Nataraja (ZP Cosim thesis)
[3] Case-statement coverage is implemented as a proof-of-concept within ZP Cosim. ©Copyright 2023 Anoop Mysore Nataraja (ZP Cosim thesis)
[4] Muxes are the sources of multiplicity in hardware states, being the fundamental functional switches (or decision statements), and the cumulative combination of toggles in mux-selects across all the muxes amount to all the different possible control paths in the hardware. ©Copyright 2023 Anoop Mysore Nataraja (ZP Cosim thesis)
[5] ZP Cosim's coverage metric implementation consists of three parts: Surelog (SystemVerilog parser/compiler), UHDM (elaborated intermediate representation), and a customizable walker that produces hierarchical instance names of coverpoints. ©Copyright 2023 Anoop Mysore Nataraja (ZP Cosim thesis)
[6] Coverpoints are assembled into the top-level wrapper of the hardware design via SystemVerilog assertions (for simulations) or dedicated coverage collection modules with memory modules (for emulations and post-processing). ©Copyright 2023 Anoop Mysore Nataraja (ZP Cosim thesis)