Overview

Case-statement coverage is a structural/code coverage metric used in hardware verification. It assesses the completeness of a test vector in exercising all the case-statement control paths in a hardware design ^[1]. The metric provides visibility into whether a given testbench has driven the design under test (DUT) through every branch of its case statements.

Role in Verification

Case-statement coverage is explicitly not a standalone metric. Rather, it serves as another perspective on one frontier of verification progress, complementing other coverage criteria such as Mux Toggle Coverage ^[1]. In the ZP Cosim framework, it appears alongside Mux Toggle Coverage as part of a broader set of automated coverage instrumentation capabilities.

Relationship to Mux Toggle Coverage

Case-statement coverage is conceptually related to Mux Toggle Coverage, which is described as similar in spirit to branch coverage in software testing. Muxes (multiplexers) are characterized as the fundamental functional switches or decision statements in hardware — i.e., the sources of multiplicity in hardware states. The cumulative combination of toggles in mux-selects across all the muxes amount to all the different possible control paths in the hardware ^[1]. Case-statement coverage targets an analogous idea at the source-language level, looking at case statements rather than elaborated mux structures.

Implementation

Case-statement coverage is implemented as a proof-of-concept within ZP Cosim, the verification infrastructure described in the 2023 University of Washington thesis by Anoop Mysore Nataraja ^[1]. The implementation shares the same automated coverage instrumentation pipeline as other metrics in ZP Cosim:

1. Surelog — an open-source SystemVerilog parser and compiler that ingests a SystemVerilog hardware description of the design and generates a walkable parse tree-like object ^[1].
2. Universal Hardware Data Model (UHDM) — the elaborated intermediate representation produced by Surelog ^[1].
3. A customizable walker — that operates on the UHDM object to produce hierarchical instance names of coverpoints for monitoring coverage ^[1].

The generated coverpoints are assembled into the top-level wrapper of the hardware design either as SystemVerilog assertions (for simulation, assessable through debug prints and waveform dumps) or as dedicated coverage collection modules with memory modules (for emulation and post-processing) ^[1]. ZP Cosim provides GNU Make routines to automatically package the identified hierarchically referenced coverpoints into coverage modules ^[1].

Status

Within the ZP Cosim framework, case-statement coverage is presented as a proof-of-concept metric ^[1], indicating it is a demonstrative implementation rather than a fully featured production coverage solution.