2026-07-10
6 items 204 entities 222 connections
Processed 22 entities and 19 relations.
ExactStep Instruction Set Simulator Instruction-Accurate Simulation Cosimulation Dynamic Binary Translation QEMU RISC-V MIPS ARM RV32IMAC RV64IMAC ARMv6-M ELF Bare-Metal Execution Instruction Trace Device Tree Blob VirtIO RISC-V Compliance Tests exactstep-riscv-linux SystemC Bus Interfacing ultraembedded cpu::step()
Processed 11 entities and 12 relations.
Processed 14 entities and 13 relations.
TheHuzz Instruction Fuzzing Golden-Reference Model Software-Exploitable Vulnerabilities TheHuzz: Instruction Fuzzing of Processors Using Golden-Reference Models for Finding Software-Exploitable Vulnerabilities Rahul Kande Addison Crump Garrett Persyn Patrick Jauernig Ahmad-Reza Sadeghi Aakash Tyagi Jeyavijayan Rajendran USENIX Association Processor Security
RISC-V Lockstep Co-Simulation: Retirement-Level Step-and-Compare for Faster Verification & Debug | by Alpinum Consulting | Medium
source →Processed 39 entities and 45 relations.
Lockstep Co-Simulation Retirement-Level Step-and-Compare Instruction Retirement Architectural State Asynchronous Events Constrained-Random Instruction Streams Directed ISA Tests Configurable State Mask Weak Memory Model Virtual Memory Operations CSR Side Effects RTL Simulation Reference Model Lockstep Co-Simulation Methodology Checkpoint-Based Regression Mismatch Reporting at Point of Failure Non-Deterministic Source Masking Seed-Based Deterministic Replay RVVI ImperasDV ImperasFPM Synopsys VCS Verdi UVM SystemVerilog RISC-V RTL General-Purpose Registers Control and Status Registers Program Counter Synopsys Imperas S. Davidmann Understanding the RISC-V Verification Ecosystem RISC-V Processor Verification Requires the Full Toolbox Co-Simulation Harness Scoreboard Functional Coverage Multi-Hart Design
Processed 49 entities and 52 relations.
Single Event Upset Soft Error Silent Data Corruption Formal Verification Model Checking Bounded Model Checking Fault Injection Simulation-Based Fault Injection Backward Tracing Forward Tracing Cone-Of-Influence Analysis State Space Explosion Memory Abstraction Strobe Properties Architectural Properties Crash Properties Hang Properties Triple Modular Redundancy Register Transfer Level XOR-Gate Fault Injection Fault Controller Module Misaligned Instructions Random Fault Injection Fault Coverage SystemVerilog Assertions Cadence JasperGold FPV JasperGold Superlint App SystemVerilog Using Formal Verification to Evaluate Single Event Upsets in a RISC-V Core Bing Xue Mark Zwolinski University of Southampton lowRISC RISC-V Ibex Core RV32IMC Instruction Set Control Status Registers Physical Memory Protection Finite State Machine Program Counter Register File Instruction FIFO ISO 26262 Fault Tree Analysis Runtime Verification AUX SystemVerilog Code Liveness Properties Safety Properties Double Event Upset
Processed 69 entities and 81 relations.
HiFuzz Hierarchical Reinforcement Learning Hardware Fuzzing Mutation-Based Fuzzing Constructive Test Generation Coverage-Guided Fuzzing Program Agent Basic Block Agent Semantic-Aware Basic Block Encoder Adaptive Coverage Reward Mechanism Intrinsic Novelty Reward Reward Sparsity Rainbow DQN Proximal Policy Optimization Random Network Distillation Masked Language Modeling Contrastive Learning Upper Confidence Bound Multi-Armed Bandit Bi-LSTM Structured RISC-V Tokenizer Basic Block Similarity Metric Constrained Random Verification Formal Verification Differential Testing RFUZZ DifuzzRTL ProcessorFuzz Cascade ChatFuzz GenHuzz Verilator Spike Cocotb Encarsia RISC-V RTL MUX Coverage Control Register Coverage Line Coverage Toggle Coverage Chisel ISA Pre-Simulation Basic Block Hierarchical Configuration Dual-Advantage Actor Loss Speculative Execution Vulnerabilities Meltdown Spectre Moore's Law GPT-2 RWKV Curriculum Learning Online Cluster-Distance Novelty Estimator Module-Level Coverage Weighting Multi-Head Actor-Critic HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing Ya Wang Hanwei Fan Zhenguo Liu Xiaofeng Zhou Yangdi Lyu Jiang Xu Wei Zhang Rocket Core BOOM Core CVA6 Structured RISC-V Tokenizer Bi-LSTM