2026-07-09
5 items 178 entities 189 connections
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Processed 29 entities and 41 relations.
Constrained Random Test (CRT) Instruction Abstraction Layer (IAL) Instruction Streamer Priority Scheduler Instruction Translator Program Instruction Streamer Noise Instruction Streamer Interrupt Service Instruction Streamer Custom Instruction Streamer Macro Instruction (MI) Atomic Instruction (AI) Order Dependent Instruction Test Case Generator (TCG) Test Manager (TM) Control Bus Master Bus Functional Model (BFM) Register Abstraction Layer (RAL) Control Command Bus Design Under Test (DUT) Interrupt Service Routine (ISR) Instruction Sequence Directed Test Bench Constrained Random Verification SystemVerilog RTL (Register Transfer Level) VMM (Verification Methodology Manual) Sun Microsystems, Inc. Polling Instruction Functional Coverage Instruction Queue ASIC (Application Specific Integrated Circuit)
Processed 49 entities and 54 relations.
Threadmill Post-Silicon Validation Bare-Metal Execution On-Platform Test Generation Pseudo-Random Test Generation Multi-Pass Consistency Checking Static Branch Generation Dual-Pass Branch Generation Off-Platform Floating-Point Operand Pre-Generation Joint Random Seed for Distributed Generation Concurrent Multi-Threaded Test-Case Generation Joint Random Collision Generation Illegal Instruction Interrupt Handler for Branch Completion Test Template Stimuli Generation Functional Verification Hardware Acceleration Platform Floating-Point Unit Verification Memory Coherence Testing Coverage Model Architectural Model Reference Model Constraint Satisfaction Problem Genesys-Pro FPgen Multi-Threaded Processor Testing Verification Plan Exerciser Image Builder Silicon Bring-Up Tape-Out Random Test Program Generation Write-Write Collision Load/Store Instruction Generation Shared Memory Multiprocessor Assertion Testing Threadmill: A Post-Silicon Exerciser for Multi-Threaded Processors Allon Adir Maxim Golubev Shimon Landa Amir Nahir Gil Shurek Vitali Sokhin Avi Ziv IBM Research - Haifa POWER7 Observability in Post-Silicon Platforms Pre-Silicon Verification Unified Pre- and Post-Silicon Verification Methodology Memory Trace for Debug Address Translation Path Generation
Processed 55 entities and 49 relations.
Genesys-Pro Genesys-Pro: Innovations in test program generation for functional processor verification Adir, A. Almog, E. Fournier, L. Marcus, E. Rimon, M. Vinov, M. Ziv, A. test program generation functional processor verification Writing Testbenches: Functional Verification of HDL Models Bergeron, J. biased random instruction generation genetic approach to automatic bias generation Bose, M. Shin, J. Rudnick, E.M. Dukes, T. Abadir, M. coverage directed test generation Bayesian network based coverage directed test generation Braun, M. Fine, S. evolutionary test program generation microprocessor design verification Corno, F. Cumani, G. Reorda, M.S. Squillero, G. Automatic Test Program Generation: A Case Study Coverage directed test generation for functional verification using Bayesian networks functional coverage Hole analysis for functional coverage data Lachish, O. Ur, S. Inductive Logic Programming Progol Muggleton, S. Cost evaluation of coverage directed test generation for the IBM mainframe Nativ, G. Mittermaier, S. IBM formal verification Microprocessor design verification by two-phase evolution of variable length tests Smith, J. Bartley, M. Fogarty, T. two-phase evolution of variable length tests A Genetic Testing Framework for Digital Integrated Circuits Yu, X. Fin, A. Fummi, F. automatic test generation RTL verification
Processed 39 entities and 40 relations.
Functional Verification Stimulus Generation Design Under Test (DUT) Architectural Knowledge Micro Architectural Knowledge Design Knowledge Test Template Instruction Generator Constraint Satisfaction Problem (CSP) Simulation-Based Verification Reference Model HDL Simulator Effect Determinator Machine Learning Classification Decision Tree Learning ID3 Algorithm C4.5 Algorithm Instruction Attributes Data Collector Data Classifier Performance Metrics Generation Failure Classification DUT Definition Design Knowledge Definer Pipeline Cache Genesys-Pro IBM Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification A. Adir Verification Apparatus Hardware Description Language (HDL) Branch Conditional (bc) Instruction Condition Register (CR) Test Program Generation Instruction Opcode Register Exception Behavior CPU Utilization