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STIMSMITH

Control Command Bus

Concept

The Control Command Bus is the shared command interface used in a constrained random test bench to apply register-oriented control instructions to a design under test (DUT) and to read back status or result registers. It is driven by a control bus master BFM for address, write data, and read/write control, with read data supplied by the DUT or a control bus slave BFM. Because the bus may be shared with other integrated circuits, verification includes injecting out-of-address-space noise commands that the DUT should ignore.

First seen 7/9/2026
Last seen 7/17/2026
Evidence 9 chunks
Wiki v2

WIKI

Overview

The Control Command Bus is the command interface used by a constrained random test (CRT) bench to exercise the control path of a design under test (DUT). In the described architecture, the bus carries control instructions used to initialize a selected DUT functional mode, trigger the DUT operation, and later read internal status or result registers to determine whether the test passed or failed.

The bus is treated as a system-level resource because it may be shared with other integrated circuits. As a result, verification is not limited to checking whether the DUT follows the bus protocol for commands addressed to it; it also checks whether the DUT ignores commands directed to other address spaces.

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NEIGHBORHOOD

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RELATIONSHIPS

6 connections
Instruction Abstraction Layer (IAL) ← uses 93% 2e
The IAL sends instructions to the control bus master BFM module which drives the control command bus.
Noise Instruction Streamer ← uses 95% 2e
The noise instruction streamer queues noise instructions that are issued on the control command bus during idle periods.
Control Bus Master Bus Functional Model (BFM) ← uses 97% 2e
The control bus master BFM applies stimuli and captures responses via the control command bus.
Noise Instruction Streamer ← uses 95% 1e
The Noise Instruction Streamer queues noise instructions to be applied on the control command bus during idle periods.
Control Bus Master BFM Module ← uses 98% 1e
The Control Bus Master BFM Module drives the address bus and control signals on the control command bus.
Control Bus Slave BFM Module ← uses 95% 1e
The Control Bus Slave BFM Module drives the data bus during read operations on the control command bus.

LINKED ENTITIES

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Instruction Abstraction Layer (IAL) USES Extracted graph relationship
Noise Instruction Streamer USES Extracted graph relationship
Control Bus Master BFM Module USES Extracted graph relationship
Control Bus Slave BFM Module USES Extracted graph relationship

CITATIONS

10 sources
10 citations — click to expand
[1] The Control Command Bus is used by a constrained random test bench to initialize the DUT, cause it to perform a selected operation, and read internal registers or status registers to determine pass/fail. METHOD AND APPARATUS FOR A CONSTRAINED RANDOM TEST BENCH - Patent application
[2] The Control Command Bus may be shared with other integrated circuits, so verification includes testing that the DUT ignores commands outside its address space. METHOD AND APPARATUS FOR A CONSTRAINED RANDOM TEST BENCH - Patent application
[3] The control bus master BFM drives the address bus and read/write control signal; the data bus is driven by the master BFM during writes and by the control bus slave BFM during reads. Method and apparatus for verifying integrated circuit design using a constrained random test bench - Oracle America, Inc.
[4] An instruction sent to the control bus master BFM may include an address value, data value, and read/write control signal value; a write example drives address 104, data 1234, and the write control indication. Method and apparatus for verifying integrated circuit design using a constrained random test bench - Oracle America, Inc.
[5] The IAL abstracts lower-level control instructions to higher-level macro instructions and can inject interrupt-service and background-noise instructions onto the control command bus. METHOD AND APPARATUS FOR A CONSTRAINED RANDOM TEST BENCH - Patent application
[6] In one embodiment, the IAL includes instruction streamers, a priority scheduler, and an instruction translator; the priority scheduler selects instructions and the translator converts them into low-level commands understood by the control bus master BFM. METHOD AND APPARATUS FOR A CONSTRAINED RANDOM TEST BENCH - Patent application
[7] The instruction translator converts high-level atomic instructions into low-level register read/write commands executed by the RAL; read operations obtain data from the DUT or slave BFM and compare it with an expected mirror value. METHOD AND APPARATUS FOR A CONSTRAINED RANDOM TEST BENCH - Patent application
[8] Typical test-case activity on the Control Command Bus follows setup busy, operation idle, and read-back busy periods. METHOD AND APPARATUS FOR A CONSTRAINED RANDOM TEST BENCH - Patent application
[9] During idle Control Command Bus periods, queued noise instructions are issued by the priority scheduler and are typically applied at random times. METHOD AND APPARATUS FOR A CONSTRAINED RANDOM TEST BENCH - Patent application
[10] Noise commands lie outside the DUT address space, simulate commands to another device sharing the Control Command Bus, and should be ignored by the DUT; they may be queued at intervals such as every 20 ms. Method and apparatus for verifying integrated circuit design using a constrained random test bench - Oracle America, Inc.