Control Bus Master Bus Functional Model (BFM)

Concept

In a constrained random test bench for control-oriented designs, the Control Bus Master BFM (Bus Functional Model) is the module that physically drives the control command bus to apply stimuli to the design under test (DUT) and to capture responses from it. It receives high-level commands from an instruction translator (typically through a Register Abstraction Layer), drives the address bus, data bus, and read/write control signal, and participates in both write operations (driving address, data, and control) and read operations (capturing data driven by the DUT or a slave BFM).

First seen 7/9/2026

Last seen 7/9/2026

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Control Bus Master Bus Functional Model (BFM)

Role in the Test Bench

In the constrained random test (CRT) test bench architecture described in U.S. patent application 20090164861, the test bench is composed of a test case generator, a test manager, a control bus master BFM module, and a control bus slave BFM module. The control bus master BFM module is the component that actually drives the control command bus to stimulate the design under test (DUT) and that captures the DUT's responses off the bus.

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NEIGHBORHOOD

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RELATIONSHIPS

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Instruction Translator ← uses 95% 2e

The instruction translator sends low-level commands to the control bus master BFM for execution on the design.

Control Command Bus uses → 97% 2e

The control bus master BFM applies stimuli and captures responses via the control command bus.

Constrained Random Test (CRT) ← uses 95% 1e

The CRT bench uses a control bus master BFM to apply stimuli to the design under test.

LINKED ENTITIES

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Constrained Random Test (CRT) USES Extracted graph relationship

Instruction Translator USES Extracted graph relationship

Control Command Bus USES Extracted graph relationship

CITATIONS

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9 citations — click to expand

[1] The test bench includes a test case generator, a test manager, a control bus master BFM module, and a control bus slave BFM module. METHOD AND APPARATUS FOR A CONSTRAINED RANDOM TEST BENCH - Patent application

[2] During a write operation the master BFM drives the address bus, data bus, and read/write control signal; during a read operation it captures data driven by the DUT or slave BFM. METHOD AND APPARATUS FOR A CONSTRAINED RANDOM TEST BENCH - Patent application

[3] The control command bus 112 typically includes an address bus, a data bus, and a read/write control signal. METHOD AND APPARATUS FOR A CONSTRAINED RANDOM TEST BENCH - Patent application

[4] Each instruction sent to the control bus master BFM may include an address value, a data value, and a read/write control signal value. METHOD AND APPARATUS FOR A CONSTRAINED RANDOM TEST BENCH - Patent application

[5] The priority scheduler selects an individual instruction from the instruction streamers and sends it to the instruction translator, which translates it into low-level commands understood by the control bus master BFM module. METHOD AND APPARATUS FOR A CONSTRAINED RANDOM TEST BENCH - Patent application

[6] The instruction translator translates high-level atomic instructions into low-level register read/write commands executed by the Register Abstraction Layer (RAL), which may be a SystemVerilog application package that maintains a mirror copy of the device's register values. METHOD AND APPARATUS FOR A CONSTRAINED RANDOM TEST BENCH - Patent application

[7] The RAL's generic read/write functions are invoked to send register access instructions to the control bus master BFM module, updating the mirror on writes and comparing expected vs. read values on reads. METHOD AND APPARATUS FOR A CONSTRAINED RANDOM TEST BENCH - Patent application

[8] During idle control command bus periods, the priority scheduler issues atomic noise instructions queued by the noise instruction streamer, applied on the bus to simulate activity from another device sharing the bus. METHOD AND APPARATUS FOR A CONSTRAINED RANDOM TEST BENCH - Patent application

[9] The control command bus alternates between busy setup periods, idle periods while the DUT operates, and busy read-back periods during a typical test case. METHOD AND APPARATUS FOR A CONSTRAINED RANDOM TEST BENCH - Patent application