Constrained Random Test (CRT)

Concept

Constrained Random Test (CRT) is a verification methodology for integrated-circuit and ASIC designs that applies randomized but valid instruction sequences to a design under test (DUT), preserving required ordering among order-dependent instructions while randomizing order-independent instructions and data values within declared constraints. A CRT test bench typically includes a test case generator, a test manager, an instruction abstraction layer (IAL) with multiple instruction streamers, a priority scheduler, an instruction translator, and a control bus master bus functional model (BFM) that drives stimuli and captures responses on a control command bus. The approach is contrasted with directed test benches and is commonly implemented using SystemVerilog-based test benches such as VMM and RAL.

First seen 7/9/2026

Last seen 7/17/2026

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Overview

A Constrained Random Test (CRT) is a verification methodology applied during simulation of integrated-circuit or ASIC designs. In the described architecture, a CRT test bench applies input stimuli to a design under test (DUT), captures output responses through a control command bus, and compares captured responses with expected responses to determine whether a test case passes or fails.

CRT is presented as an alternative to traditional directed test benches. A directed test bench applies fixed sequences of test vectors and is typically programmed with the exact register-access sequence of instructions issued to the DUT via a control command bus. Because the register-access sequence can vary due to interrupts or because multiple functional units share the same control command bus, generating every possible directed sequence by hand is time-consuming and may leave coverage incomplete. CRT addresses this by randomizing valid sequences within declared constraints.

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RELATIONSHIPS

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Test Manager (TM) uses → 95% 2e

The CRT bench includes a test manager that starts and stops instruction streamers.

Priority Scheduler uses → 95% 2e

The CRT bench includes a priority scheduler to sequence instruction sequences from multiple streamers.

Randomized Instruction Sequence uses → 97% 2e

The CRT methodology randomizes instruction sequences within specified constraint boundaries.

Instruction Abstraction Layer (IAL) uses → 97% 2e

The CRT test bench employs an instruction abstraction layer to create and execute constrained random tests.

Control Bus Master Bus Functional Model (BFM) uses → 95% 1e

The CRT bench uses a control bus master BFM to apply stimuli to the design under test.

Constrained Random Verification ← uses 93% 1e

Constrained random verification is the methodology implemented by the CRT test bench focused on the control path of the DUT.

VMM (Verification Methodology Manual) uses → 90% 1e

One embodiment of the CRT bench is based on a VMM and RAL-based SystemVerilog test bench.

Directed Test Bench compares with → 90% 1e

Traditional directed test bench methods are less efficient at finding design errors compared to constrained random test benches as designs grow in complexity.

CRT Test Bench ← implements 99% 1e

The CRT Test Bench implements the constrained random test methodology for verifying integrated circuit designs.

Functional Coverage uses → 88% 1e

One challenge of CRT is collecting functional coverage for complex instruction sequences.

SystemVerilog uses → 97% 1e

The CRT test bench architecture is built on SystemVerilog.

Instruction Translator uses → 95% 1e

The CRT bench includes an instruction translator to apply issued instructions to the integrated circuit design.

Test Case Generator (TCG) uses → 95% 1e

The CRT bench includes a test case generator to generate test cases.

LINKED ENTITIES

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CRT Test Bench IMPLEMENTS Extracted graph relationship

Randomized Instruction Sequence USES Extracted graph relationship

Functional Coverage USES Extracted graph relationship

CITATIONS

12 sources

12 citations — click to expand

[1] A CRT test bench applies input stimuli to a design under test, captures responses on a control command bus, and compares them with expected responses to determine whether a test case passes or fails. METHOD AND APPARATUS FOR A CONSTRAINED RANDOM TEST BENCH

[2] A directed test bench applies fixed sequences of test vectors and may be inefficient when interrupt routines or shared control-command-bus traffic cause many sequence variations. METHOD AND APPARATUS FOR A CONSTRAINED RANDOM TEST BENCH

[3] A CRT test case contains a valid program instruction sequence and constraints that specify valid data ranges, order-dependent instruction positions, and a seed for reproducibility. METHOD AND APPARATUS FOR A CONSTRAINED RANDOM TEST BENCH

[4] The CRT architecture includes a test case generator, test manager, instruction abstraction layer with program, noise, interrupt-service, and custom instruction streamers, a priority scheduler, an instruction translator, and a control bus master BFM. METHOD AND APPARATUS FOR A CONSTRAINED RANDOM TEST BENCH

[5] Each macro instruction is translated into one or more atomic instructions, which are the smallest instruction unit managed by the scheduler and applied to the DUT in order without interruption. Method and apparatus for verifying integrated circuit design using a constrained random test bench - Oracle America, Inc.

[6] The priority scheduler issues atomic instructions from the highest-priority streamer with queued work, allowing each atomic instruction to complete before issuing the next; interrupt streams may queue in response to interrupt events. Method and apparatus for verifying integrated circuit design using a constrained random test bench - Oracle America, Inc.

[7] In one embodiment, streamers are prioritized from highest to lowest as custom, interrupt service, program, and noise; priority may vary by embodiment and by test case. Method and apparatus for verifying integrated circuit design using a constrained random test bench - Oracle America, Inc.

[8] Noise instructions are injected outside the DUT address space, including during idle control-bus periods, to test that the design ignores commands that should not affect it. METHOD AND APPARATUS FOR A CONSTRAINED RANDOM TEST BENCH

[9] An interrupt service instruction streamer issues an interrupt service routine after a random delay from interrupt detection to simulate asynchronous interrupt handling. METHOD AND APPARATUS FOR A CONSTRAINED RANDOM TEST BENCH

[10] A custom instruction streamer can issue a valid randomized instruction sequence at a specified simulation time, inserted immediately after the priority scheduler finishes the current instruction. METHOD AND APPARATUS FOR A CONSTRAINED RANDOM TEST BENCH

[11] Functional coverage for complex instruction sequences, including CRC verification across an entire memory, is one of the verification challenges the methodology addresses. METHOD AND APPARATUS FOR A CONSTRAINED RANDOM TEST BENCH

[12] One embodiment of the CRT bench architecture is based on a VMM and RAL SystemVerilog test bench, although the architecture can be used with other test benches as well. METHOD AND APPARATUS FOR A CONSTRAINED RANDOM TEST BENCH