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Constrained Random Test (CRT)

Concept WIKI v2 · 7/17/2026

Constrained Random Test (CRT) is a verification methodology for integrated-circuit and ASIC designs that applies randomized but valid instruction sequences to a design under test (DUT), preserving required ordering among order-dependent instructions while randomizing order-independent instructions and data values within declared constraints. A CRT test bench typically includes a test case generator, a test manager, an instruction abstraction layer (IAL) with multiple instruction streamers, a priority scheduler, an instruction translator, and a control bus master bus functional model (BFM) that drives stimuli and captures responses on a control command bus. The approach is contrasted with directed test benches and is commonly implemented using SystemVerilog-based test benches such as VMM and RAL.

Overview

A Constrained Random Test (CRT) is a verification methodology applied during simulation of integrated-circuit or ASIC designs. In the described architecture, a CRT test bench applies input stimuli to a design under test (DUT), captures output responses through a control command bus, and compares captured responses with expected responses to determine whether a test case passes or fails.

CRT is presented as an alternative to traditional directed test benches. A directed test bench applies fixed sequences of test vectors and is typically programmed with the exact register-access sequence of instructions issued to the DUT via a control command bus. Because the register-access sequence can vary due to interrupts or because multiple functional units share the same control command bus, generating every possible directed sequence by hand is time-consuming and may leave coverage incomplete. CRT addresses this by randomizing valid sequences within declared constraints.

Core idea

A CRT test case contains a valid program instruction sequence together with constraints. Constraints can:

  • Define valid data ranges, such as source and destination address ranges, and valid data values within those ranges.
  • Preserve order dependencies among instructions, so that order-dependent instructions remain in their required positions while order-independent instructions and data values are randomized within the constraints.

The randomized sequence remains valid because order-sensitive relationships are maintained; only order-independent instructions and data values are randomized. A seed may be specified so that the same randomized sequence can be regenerated later by reusing the same seed.

For example, a program instruction sequence may require a reset-like instruction first and a go-like instruction last, while allowing intermediate instructions to appear in randomized order. The program instruction streamer generates a constrained-random version of the sequence by preserving the order-sensitive relationships and randomizing only the order-independent instructions.

Architecture

The described CRT test bench includes these major components:

  • Test Case Generator (TCG): generates test cases. A test case can include a valid program instruction sequence for a particular DUT mode, constraints on values or ordering, an interrupt service routine instruction sequence, and an indication that noise instructions should be sent when the control command bus is idle.
  • Test Manager (TM): receives test cases for execution, analyzes them, selects the instruction streamers needed, instructs selected streamers to issue instruction streams, and may halt a streamer during execution when the test case requires it.
  • Instruction Abstraction Layer (IAL): allows test cases to be generated using higher-level macro instructions rather than lower-level HDL or RTL-level instructions. It abstracts lower-level control instructions into macro instructions and automates generation of valid random program instruction sequences.
  • Instruction streamers: independently generate or queue instruction streams. The described IAL may include program, noise, interrupt-service, and custom instruction streamers.
  • Priority Scheduler: selects an individual instruction from the available streamers according to a priority scheme and issues instructions one at a time. Each atomic instruction is allowed to complete before the next atomic instruction is selected and forwarded for translation and low-level execution.
  • Instruction Translator: translates selected instructions into one or more low-level commands understood by the control bus master BFM.
  • Control Bus Master BFM: applies stimuli to the DUT and captures responses during bus transactions. A corresponding control bus slave BFM participates in register write and read operations on the control command bus.

Instruction abstraction

The IAL allows test writers to work with macro instructions instead of low-level register-transfer-level control details. A macro instruction can represent a bus operation using values such as an address, a data value, and a read/write control signal. The instruction translator then converts the selected instruction into low-level hardware commands that the control bus master BFM can execute.

This abstraction is useful for control-oriented designs because some control instructions must be applied in a specific order to initialize or program a desired function, while other instructions in the same sequence may be order-independent. The IAL automates the process of generating a valid random program instruction sequence and supports injecting other sequences onto the control command bus during execution.

Atomic vs. macro instructions

Each instruction streamer translates each macro instruction (MI) of its instruction sequence into one or more atomic instructions (AIs) to form an AI instruction sequence. In one embodiment, each MI represents a fixed sequence of one or more AI instructions. An AI is the smallest instruction unit (primitive) managed by the program scheduler and, when translated by the instruction translator, is a set of low-level instructions (such as register-level read/write commands) that are applied to the DUT in order without interruption. The priority scheduler generally allows each AI to complete before transferring another AI to the instruction translator.

Randomization and injection scenarios

The described CRT architecture supports several constrained-random control-path scenarios:

  1. Valid sequence randomization: order-dependent instructions remain ordered, while order-independent instructions and data values can be randomized within constraints.
  2. Noise injection: noise instructions that lie outside the DUT address space can be inserted, including during idle control-bus periods, to test whether the design ignores commands that should not affect it.
  3. Interrupt service routine injection: an interrupt service instruction streamer can issue an interrupt service routine after a random delay from interrupt detection, simulating asynchronous interrupt handling.
  4. Custom sequence injection: a custom instruction streamer can issue a valid randomized instruction sequence at a specified simulation time.
  5. Priority-based sequencing: multiple instruction queues or streamers can be sequenced according to priority; a higher-priority sequence can execute after the currently executing instruction completes.
  6. Polling management and functional coverage: the framework can manage polling instructions and collect functional coverage for complex instruction sequences, including cyclic-redundancy-check verification across an entire memory of the chip design.

Priority scheme

Each instruction streamer may have a specified priority, so that a higher-priority streamer is serviced by the priority scheduler before a lower-priority streamer. In one embodiment, the streamers are prioritized from highest to lowest as: custom instruction streamer, interrupt service instruction streamer, program instruction streamer, and noise instruction streamer. Other embodiments may prioritize the streamers differently and may allow the priority of the streamers to change on a test-case-by-test-case basis.

The priority scheduler typically issues an atomic instruction from the highest-priority streamer that has an instruction queued and awaiting execution, waits for the instruction translator to finish executing that atomic instruction, and then issues the next atomic instruction from the highest-priority streamer that has one awaiting execution. Queuing of certain instruction streams, such as an interrupt service instruction stream, may occur in response to events such as an interrupt.

Relationship to SystemVerilog, VMM, and RAL

The patent describes the CRT bench architecture as being buildable on SystemVerilog, described there as a unified language for hardware design, specification, and verification. One embodiment is based on a VMM and RAL SystemVerilog test bench, although the source states that the architecture can be used with other test benches as well.

Verification challenges addressed

The source material identifies the following challenges that a constrained-random control-path methodology must address: randomizing a valid instruction sequence while preserving the order of order-dependent instructions; randomly injecting noise instructions that lie outside the address space of the design; injecting an interrupt service routine instruction sequence after a random delay to simulate interrupt handling; injecting a specific instruction sequence at a specific time; managing a polling instruction; prioritizing instruction sequences; and collecting functional coverage for complex instruction sequences.

LINKED ENTITIES

3 links
CRT Test Bench IMPLEMENTS
Randomized Instruction Sequence USES
Functional Coverage USES

CITATIONS

12 sources
12 citations
[1] A CRT test bench applies input stimuli to a design under test, captures responses on a control command bus, and compares them with expected responses to determine whether a test case passes or fails. METHOD AND APPARATUS FOR A CONSTRAINED RANDOM TEST BENCH
[2] A directed test bench applies fixed sequences of test vectors and may be inefficient when interrupt routines or shared control-command-bus traffic cause many sequence variations. METHOD AND APPARATUS FOR A CONSTRAINED RANDOM TEST BENCH
[3] A CRT test case contains a valid program instruction sequence and constraints that specify valid data ranges, order-dependent instruction positions, and a seed for reproducibility. METHOD AND APPARATUS FOR A CONSTRAINED RANDOM TEST BENCH
[4] The CRT architecture includes a test case generator, test manager, instruction abstraction layer with program, noise, interrupt-service, and custom instruction streamers, a priority scheduler, an instruction translator, and a control bus master BFM. METHOD AND APPARATUS FOR A CONSTRAINED RANDOM TEST BENCH
[5] Each macro instruction is translated into one or more atomic instructions, which are the smallest instruction unit managed by the scheduler and applied to the DUT in order without interruption. Method and apparatus for verifying integrated circuit design using a constrained random test bench - Oracle America, Inc.
[6] The priority scheduler issues atomic instructions from the highest-priority streamer with queued work, allowing each atomic instruction to complete before issuing the next; interrupt streams may queue in response to interrupt events. Method and apparatus for verifying integrated circuit design using a constrained random test bench - Oracle America, Inc.
[7] In one embodiment, streamers are prioritized from highest to lowest as custom, interrupt service, program, and noise; priority may vary by embodiment and by test case. Method and apparatus for verifying integrated circuit design using a constrained random test bench - Oracle America, Inc.
[8] Noise instructions are injected outside the DUT address space, including during idle control-bus periods, to test that the design ignores commands that should not affect it. METHOD AND APPARATUS FOR A CONSTRAINED RANDOM TEST BENCH
[9] An interrupt service instruction streamer issues an interrupt service routine after a random delay from interrupt detection to simulate asynchronous interrupt handling. METHOD AND APPARATUS FOR A CONSTRAINED RANDOM TEST BENCH
[10] A custom instruction streamer can issue a valid randomized instruction sequence at a specified simulation time, inserted immediately after the priority scheduler finishes the current instruction. METHOD AND APPARATUS FOR A CONSTRAINED RANDOM TEST BENCH
[11] Functional coverage for complex instruction sequences, including CRC verification across an entire memory, is one of the verification challenges the methodology addresses. METHOD AND APPARATUS FOR A CONSTRAINED RANDOM TEST BENCH
[12] One embodiment of the CRT bench architecture is based on a VMM and RAL SystemVerilog test bench, although the architecture can be used with other test benches as well. METHOD AND APPARATUS FOR A CONSTRAINED RANDOM TEST BENCH

VERSION HISTORY

v2 · 7/17/2026 · minimax/minimax-m3 (current)
v1 · 7/9/2026 · gpt-5.5