2026-07-08
3 items 86 entities 97 connections
Processed 17 entities and 23 relations.
Model-Based Test-Generator Constraint Satisfaction Automatic Test Program Generation Memory Access Generation Address Constraint Satisfaction Addressing Modes Complex Addressing Modes PowerPC Architecture x86 Architecture Constraint satisfaction for test program generation Daniel R. Lewin Laurent Sébastien Fournier Moshe Levinger E. Roytman Gil Shurek IBM Research - Haifa Constraint-Based Automatic Test Data Generation
Processed 54 entities and 56 relations.
functional verification dynamic verification random test generation test template dynamic interleaving of test templates combined test case design-under-verification coverage criteria transaction sparseness unbreakable section baseline template weighted template selection cache operations direct memory access CPU-initiated memory access prologue section epilogue section global knowledge base inter-scenario event address collision multiprocessor verification test generator template arbitrator unit execution engine design verification system constraint satisfaction for test program generation model-based test generation user-defined coverage on-the-fly test generation stimulus injection User Defined Coverage—A Tool Supported Methodology for Design Verification Model-Based Test Generation For Processor Design Verification Constraint Satisfaction for Test Program Generation Test Program Generation for Functional Verification of PowerPC Processors in IBM Adaptive Test Program Generation (US 2003/0130813 A1) Raanan Grinwald Eran Harel Michael Orgad Shmuel Ur Avi Ziv Y. Lichtenstein Y. Malka A. Aharon L. Fournier D. Lewin M. Levinger E. Roytman Gil Shurek GenerateSingleTransaction pseudocode WeightedChoice pseudocode CPU processor simulation RTL
Processed 15 entities and 18 relations.