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Cache Operations

Concept

Cache operations refer to memory access functions performed by processors (e.g., CPU-initiated reads/writes that target cached memory regions). In hardware design verification, cache operations are commonly exercised by test templates and combined with operations from other subsystems (such as DMA from I/O devices) to produce combined test cases that expose inter-scenario events like address collisions.

First seen 7/8/2026
Last seen 7/8/2026
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Cache Operations

Definition in Verification Context

In the context of hardware design verification, cache operations denote the memory access functions issued by processors that interact with the cache hierarchy of a design-under-verification (DUV). They are treated as one of the distinct functions of a processor-based design that can be targeted by an individual test template and exercised as part of a generated test case [1].

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RELATIONSHIPS

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combined test case ← uses 90% 1e
A combined test case can target cache operations for processors while simultaneously testing direct memory accesses.

CITATIONS

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[1] Cache operations are memory access functions issued by processors and represent a distinct function of a processor-based design that can be targeted by an individual test template. US7627843B2 - Dynamically interleaving randomly generated test cases
[2] A canonical example of a combined test case is one that targets cache operations for processors while simultaneously testing DMA coming from an I/O device. US7627843B2 - Dynamically interleaving randomly generated test cases
[3] An inter-scenario event arising from combining cache-operation templates with other templates is the generation of address collisions between CPU accesses to memory and DMAs targeting the same memory addresses. US7627843B2 - Dynamically interleaving randomly generated test cases
[4] Cache-operation test templates can be reused across design variants and combined with new templates, with the resulting interleaving governed by user-assigned relative weights. US7627843B2 - Dynamically interleaving randomly generated test cases