Address Constraint Satisfaction

Technique

Address Constraint Satisfaction is a technique for automatic test program generation that solves constraints governing memory access generation. It was introduced and formalized within the Model-Based Test-Generator (MBTG) framework, and supports complex addressing modes used in architectures such as PowerPC and x86.

First seen 7/8/2026

Last seen 7/8/2026

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Address Constraint Satisfaction

Overview

Address Constraint Satisfaction is a technique used in automatic test program generation. It addresses the central problem of solving constraints for memory access generation by providing a generic algorithmic framework that decides how generated memory accesses should be resolved against architectural addressing rules. The technique was introduced by Lewin, Fournier, Levinger, Roytman, and Shurek at IBM Research - Haifa in their 2002 paper "Constraint satisfaction for test program generation."

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RELATIONSHIPS

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Constraint satisfaction for test program generation ← introduces 95% 1e

The paper describes a framework and algorithm for address constraint satisfaction.

Model-Based Test-Generator ← implements 97% 1e

The described algorithm has been implemented in the Model-Based Test-Generator tool.

Complex Addressing Modes uses → 96% 1e

The address constraint satisfaction algorithm handles complex addressing modes.

PowerPC Architecture uses → 95% 1e

The algorithm handles complex addressing modes specifically in the PowerPC architecture.

x86 Architecture uses → 95% 1e

The algorithm handles complex addressing modes specifically in the x86 architecture.

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Constraint satisfaction for test program generation INTRODUCES Extracted graph relationship

Model-Based Test-Generator IMPLEMENTS Extracted graph relationship

Complex Addressing Modes USES Extracted graph relationship

PowerPC Architecture USES Extracted graph relationship

x86 Architecture USES Extracted graph relationship

CITATIONS

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[1] Address Constraint Satisfaction was introduced in the 2002 paper 'Constraint satisfaction for test program generation' by Lewin, Fournier, Levinger, Roytman, and Shurek. Constraint satisfaction for test program generation

[2] The central problem the technique solves is solving constraints for memory access generation. Constraint satisfaction for test program generation

[3] The technique is implemented in the Model-Based Test-Generator. Constraint satisfaction for test program generation

[4] The algorithm handles complex addressing modes in PowerPC, x86, and other architectures. Constraint satisfaction for test program generation

[5] The framework allows flexibility in modeling new addressing modes. Constraint satisfaction for test program generation