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Complex Addressing Modes

Concept

Complex addressing modes refer to memory access patterns used in modern instruction set architectures (such as PowerPC and x86) whose structure combines multiple components—base registers, index registers, displacement values, and scaling factors—in ways that complicate automatic generation of valid memory accesses. They are a key target of address constraint satisfaction algorithms used in test program generation.

First seen 7/8/2026
Last seen 7/8/2026
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Complex Addressing Modes

Definition and Scope

In instruction set architectures such as PowerPC and x86, memory operands are described by addressing modes that specify how an effective address is computed from register and constant components. Many of these modes are complex because they combine several operands—base registers, index registers, scaled indices, and displacements—into a single effective address computation. The precise set of components and the rules for combining them are architecture-specific.

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RELATIONSHIPS

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Address Constraint Satisfaction ← uses 96% 1e
The address constraint satisfaction algorithm handles complex addressing modes.
Addressing Modes part of → 90% 1e
Complex addressing modes are a subset of addressing modes in general.

CITATIONS

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3 citations — click to collapse
[1] Complex addressing modes exist in modern architectures such as PowerPC and x86, and their complexity complicates automatic generation of memory accesses. Constraint satisfaction for test program generation
[2] A generic address constraint satisfaction algorithm implemented in the Model-Based Test-Generator handles complex addressing modes for PowerPC, x86, and other architectures, and allows flexibility for modeling new addressing modes. Constraint satisfaction for test program generation
[3] Solving constraints for memory access generation is a central problem in automatic test generation. Constraint satisfaction for test program generation