Complex Addressing Modes

Definition and Scope

In instruction set architectures such as PowerPC and x86, memory operands are described by addressing modes that specify how an effective address is computed from register and constant components. Many of these modes are complex because they combine several operands—base registers, index registers, scaled indices, and displacements—into a single effective address computation. The precise set of components and the rules for combining them are architecture-specific.

Role in Test Program Generation

Complex addressing modes are particularly relevant to automatic test generation. When a test program generator must synthesize memory accesses that satisfy a set of constraints (e.g., a load must read from a specific address, or two accesses must target the same or adjacent memory locations), the generator must be able to encode those constraints using whatever addressing modes the target architecture provides. Because complex modes involve multiple interacting components, solving for them is a constraint satisfaction problem rather than a simple substitution.

Relationship to Address Constraint Satisfaction

A generic algorithm for address constraint satisfaction has been implemented in the Model-Based Test-Generator (MBTG). The algorithm is designed to be flexible: it can be extended to new addressing modes without requiring a complete rewrite, so that architectures with very different addressing mode structures can be supported. As of its publication, the algorithm handled address constraint satisfaction for complex addressing modes in PowerPC, x86, and other architectures.

See Also

• Addressing Modes — the broader category of operand-addressing schemes in instruction set architectures; complex addressing modes are a subset or specialized form within this category.
• Address Constraint Satisfaction — the technique used to generate valid memory accesses that meet test-program requirements, which must specifically support complex addressing modes.