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Atomic Instruction (AI)

Concept

An Atomic Instruction (AI) is the smallest instruction unit, or primitive, managed by the priority scheduler in the Instruction Abstraction Layer of a constrained-random test bench. Instruction streamers translate each Macro Instruction (MI) into one or more AIs; the priority scheduler dispatches AIs one at a time to the instruction translator, which translates them into lower-level register read/write operations against the DUT.

First seen 7/9/2026
Last seen 7/17/2026
Evidence 8 chunks
Wiki v2

WIKI

Atomic Instruction (AI)

Definition

An Atomic Instruction (AI) is the smallest instruction unit, or primitive, managed by the priority scheduler in the Instruction Abstraction Layer (IAL) of a constrained-random test bench. Each AI is a high-level atomic operation that, when handled by the instruction translator, typically becomes a set of lower-level instructions such as register-level read/write commands applied to the Design Under Test (DUT) in order and without interruption. [C1]

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RELATIONSHIPS

6 connections
Instruction Translator ← uses 95% 2e
The instruction translator translates atomic instructions into one or more low-level hardware commands.
Macro Instruction (MI) derived from → 95% 1e
Atomic instructions are produced by translating macro instructions; each MI maps to one or more AIs.
Priority Scheduler ← uses 98% 1e
The Priority Scheduler issues and manages Atomic Instructions one at a time.
Instruction Translator ← uses 98% 1e
The Instruction Translator translates Atomic Instructions into low-level register read/write commands.
Interrupt Service Instruction Streamer ← uses 95% 1e
The Interrupt Service Instruction Streamer translates MIs into AI instruction sequences.
Macro Instruction (MI) part of → 97% 1e
Each MI is translated into one or more Atomic Instructions (AIs).

LINKED ENTITIES

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Priority Scheduler USES Extracted graph relationship
Instruction Translator USES Extracted graph relationship
Interrupt Service Instruction Streamer USES Extracted graph relationship
Macro Instruction (MI) PART_OF Extracted graph relationship

CITATIONS

10 sources
10 citations — click to expand
[1] An AI is the smallest instruction unit managed by the scheduler, and when translated it typically becomes low-level register read/write commands applied to the DUT in order without interruption. Method and apparatus for verifying integrated circuit design using a constrained random test bench - Oracle America, Inc.
[2] Instruction streamers translate each MI into one or more AIs to form an AI instruction sequence; in one embodiment each MI represents a fixed sequence of one or more AIs. Method and apparatus for verifying integrated circuit design using a constrained random test bench - Oracle America, Inc.
[3] Some MIs correspond to one AI, while a polling MI may expand into hundreds of atomic register read instructions RD1 through RDn. Method and apparatus for verifying integrated circuit design using a constrained random test bench - Oracle America, Inc.
[4] After MIs are translated into AIs, the program instruction streamer may queue the entire AI sequence for execution, and the AI sequence may be stored in a queue monitored by the priority scheduler. Method and apparatus for verifying integrated circuit design using a constrained random test bench - Oracle America, Inc.
[5] The priority scheduler selects an AI from the highest-priority streamer with queued work, transfers it to the instruction translator, and waits for the translator to finish before issuing another AI. Method and apparatus for verifying integrated circuit design using a constrained random test bench - Oracle America, Inc.
[6] One described priority order is custom, interrupt service, program, and noise instruction streamers, though other embodiments may use different or per-test priorities. Method and apparatus for verifying integrated circuit design using a constrained random test bench - Oracle America, Inc.
[7] When an interrupt-service streamer has higher priority, the scheduler dispatches ISR AIs after the current program AI completes, drains the ISR queue, then resumes remaining program AIs. Method and apparatus for verifying integrated circuit design using a constrained random test bench - Oracle America, Inc.
[8] In the FIG. 10 example, an ISR sequence queued during execution of RD2 is dispatched immediately after RD2 completes, and the program AI sequence resumes afterward. Method and apparatus for verifying integrated circuit design using a constrained random test bench - Oracle America, Inc.
[9] The instruction translator translates individual high-level AIs into low-level register read/write commands executed by the RAL; write AIs update a mirror and read AIs compare returned values with expected mirror values. Method and apparatus for verifying integrated circuit design using a constrained random test bench - Oracle America, Inc.
[10] Noise instruction streamers may queue atomic noise instructions at random times, and the priority scheduler typically issues them during idle control-command-bus periods. Method and apparatus for verifying integrated circuit design using a constrained random test bench - Oracle America, Inc.