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Atomic Instruction (AI)

Concept WIKI v2 · 7/17/2026

An Atomic Instruction (AI) is the smallest instruction unit, or primitive, managed by the priority scheduler in the Instruction Abstraction Layer of a constrained-random test bench. Instruction streamers translate each Macro Instruction (MI) into one or more AIs; the priority scheduler dispatches AIs one at a time to the instruction translator, which translates them into lower-level register read/write operations against the DUT.

Atomic Instruction (AI)

Definition

An Atomic Instruction (AI) is the smallest instruction unit, or primitive, managed by the priority scheduler in the Instruction Abstraction Layer (IAL) of a constrained-random test bench. Each AI is a high-level atomic operation that, when handled by the instruction translator, typically becomes a set of lower-level instructions such as register-level read/write commands applied to the Design Under Test (DUT) in order and without interruption. [C1]

Relationship to Macro Instructions

AIs are produced from Macro Instructions (MIs). Each instruction streamer may translate each MI in an instruction sequence into one or more AIs, forming an AI instruction sequence. In one exemplary embodiment, each MI represents a fixed sequence of one or more AIs. [C2]

The relationship is not always one-to-one:

  • A simple register read or write MI may correspond to a single AI.
  • A more complex MI may expand into many AIs. For example, macro instruction MI B is described as a polling instruction that may consist of hundreds of atomic register read instructions, RD1 through RDn. [C3]

After translation, the program instruction streamer may queue the entire AI sequence for execution by the priority scheduler; in one embodiment, the sequence is stored in a queue monitored by the scheduler. [C4]

Scheduling Semantics

The priority scheduler dispatches AIs from instruction streamer queues to the instruction translator. It typically selects an AI from the highest-priority instruction streamer that has an instruction queued and waiting, transfers that AI to the instruction translator, and waits for execution to finish before selecting another AI. [C5]

This makes the AI the scheduling boundary: the scheduler generally allows the current AI to complete before transferring the next AI for translation and lower-level execution. [C1]

In one described priority ordering, instruction streamers are prioritized from highest to lowest as follows:

  1. Custom instruction streamer
  2. Interrupt service instruction streamer
  3. Program instruction streamer
  4. Noise instruction streamer

Other embodiments may use different priorities or change priorities per test case. [C6]

Interaction with Interrupt-Service Sequences

Interrupt-service instruction streamers can queue interrupt service routine (ISR) sequences made of AIs. If an interrupt-service instruction streamer has higher priority than the program instruction streamer, the priority scheduler switches to the ISR sequence after the currently executing AI completes, not in the middle of that AI. It then issues ISR AIs until the ISR queue is empty and resumes the pending program AIs afterward. [C7]

A detailed example describes an interrupt detected during execution of AI D. After a random delay, the ISR sequence is queued while RD2 from the program AI sequence is executing. Because the interrupt-service streamer has higher priority, the scheduler transfers ISR AIs F, G, and H immediately after RD2 completes; after the ISR sequence runs, the scheduler resumes the pending program AIs RD3 through RDn, AI C, and AI E. [C8]

Execution by the Instruction Translator and RAL

The instruction translator translates individual high-level AIs into low-level register read/write commands executed by the Register Abstraction Layer (RAL). In the described embodiment, write-type AIs invoke a write function that performs a DUT register write and updates the mirror value; read-type AIs invoke a read function that compares returned data against the expected register value stored in the mirror. [C9]

Role in Test-Bench Interleaving

Because AIs are the units selected by the priority scheduler, program, interrupt-service, and noise activity can be interleaved at AI boundaries. This enables asynchronous-style scenarios such as ISR insertion during a partially executed program stream and noise instructions during idle control-command-bus periods, while still preserving completion of each dispatched AI before the next dispatch. [C5] [C7] [C10]

Related Concepts

  • Macro Instruction (MI): Higher-level instruction translated into one or more AIs.
  • Priority Scheduler: Selects and dispatches queued AIs from instruction streamers according to priority.
  • Instruction Translator: Translates AIs into lower-level register read/write operations.
  • Interrupt Service Instruction Streamer: Queues ISR sequences made of AIs, optionally after a random delay following an interrupt.

LINKED ENTITIES

4 links
Priority Scheduler USES
Instruction Translator USES
Interrupt Service Instruction Streamer USES
Macro Instruction (MI) PART_OF

CITATIONS

10 sources
10 citations
[1] An AI is the smallest instruction unit managed by the scheduler, and when translated it typically becomes low-level register read/write commands applied to the DUT in order without interruption. Method and apparatus for verifying integrated circuit design using a constrained random test bench - Oracle America, Inc.
[2] Instruction streamers translate each MI into one or more AIs to form an AI instruction sequence; in one embodiment each MI represents a fixed sequence of one or more AIs. Method and apparatus for verifying integrated circuit design using a constrained random test bench - Oracle America, Inc.
[3] Some MIs correspond to one AI, while a polling MI may expand into hundreds of atomic register read instructions RD1 through RDn. Method and apparatus for verifying integrated circuit design using a constrained random test bench - Oracle America, Inc.
[4] After MIs are translated into AIs, the program instruction streamer may queue the entire AI sequence for execution, and the AI sequence may be stored in a queue monitored by the priority scheduler. Method and apparatus for verifying integrated circuit design using a constrained random test bench - Oracle America, Inc.
[5] The priority scheduler selects an AI from the highest-priority streamer with queued work, transfers it to the instruction translator, and waits for the translator to finish before issuing another AI. Method and apparatus for verifying integrated circuit design using a constrained random test bench - Oracle America, Inc.
[6] One described priority order is custom, interrupt service, program, and noise instruction streamers, though other embodiments may use different or per-test priorities. Method and apparatus for verifying integrated circuit design using a constrained random test bench - Oracle America, Inc.
[7] When an interrupt-service streamer has higher priority, the scheduler dispatches ISR AIs after the current program AI completes, drains the ISR queue, then resumes remaining program AIs. Method and apparatus for verifying integrated circuit design using a constrained random test bench - Oracle America, Inc.
[8] In the FIG. 10 example, an ISR sequence queued during execution of RD2 is dispatched immediately after RD2 completes, and the program AI sequence resumes afterward. Method and apparatus for verifying integrated circuit design using a constrained random test bench - Oracle America, Inc.
[9] The instruction translator translates individual high-level AIs into low-level register read/write commands executed by the RAL; write AIs update a mirror and read AIs compare returned values with expected mirror values. Method and apparatus for verifying integrated circuit design using a constrained random test bench - Oracle America, Inc.
[10] Noise instruction streamers may queue atomic noise instructions at random times, and the priority scheduler typically issues them during idle control-command-bus periods. Method and apparatus for verifying integrated circuit design using a constrained random test bench - Oracle America, Inc.

VERSION HISTORY

v2 · 7/17/2026 · gpt-5.5 (current)
v1 · 7/9/2026 · minimax/minimax-m3