riscv-isa-sim (Spike)

Tool

Spike (riscv-isa-sim) is an open-source RISC-V instruction set simulator maintained by the riscv-software-src organization. Written in C, it provides a reference functional simulator of the RISC-V ISA used for ISA testing, software bring-up, and as a baseline for comparing other RISC-V simulators such as Swimmer-RISCV.

First seen 7/10/2026

Last seen 7/10/2026

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riscv-isa-sim (Spike)

Overview

Spike, hosted in the riscv-software-src/riscv-isa-sim repository, is the reference RISC-V instruction set simulator distributed by the official RISC-V software organization. The project is widely used as a functional (ISA-level) reference model for RISC-V cores and software stacks.

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NEIGHBORHOOD

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RELATIONSHIPS

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Instruction Set Simulator implements → 100% 1e

riscv-isa-sim (Spike) is described as a RISC-V simulator, implementing the Instruction Set Simulator concept.

RISC-V implements → 95% 1e

riscv-isa-sim (Spike) is a RISC-V simulator, implementing the RISC-V ISA.

Swimmer-RISCV compares with → 80% 1e

Swimmer-RISCV and riscv-isa-sim (Spike) are both RISC-V instruction set simulators described together for comparison.

LINKED ENTITIES

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Instruction Set Simulator IMPLEMENTS Extracted graph relationship

RISC-V IMPLEMENTS Extracted graph relationship

Swimmer-RISCV COMPARES_WITH Extracted graph relationship

CITATIONS

3 sources

3 citations — click to collapse

[1] Spike is the RISC-V ISA Simulator maintained by riscv-software-src on GitHub. riscv-software-src/riscv-isa-sim

[2] Spike is characterized as a very fast and simple RISC-V simulator and is used as a reference point when comparing with Swimmer-RISCV. msyksphinz-self/swimmer_riscv

[3] The riscv-isa-sim GitHub repository reports 3,165 stars, 1,078 forks, primary language C, and last updated 2026-07-10. riscv-software-src/riscv-isa-sim