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STIMSMITH

riscv-isa-sim (Spike)

Tool WIKI v1 · 7/10/2026

Spike (riscv-isa-sim) is an open-source RISC-V instruction set simulator maintained by the riscv-software-src organization. Written in C, it provides a reference functional simulator of the RISC-V ISA used for ISA testing, software bring-up, and as a baseline for comparing other RISC-V simulators such as Swimmer-RISCV.

riscv-isa-sim (Spike)

Overview

Spike, hosted in the riscv-software-src/riscv-isa-sim repository, is the reference RISC-V instruction set simulator distributed by the official RISC-V software organization. The project is widely used as a functional (ISA-level) reference model for RISC-V cores and software stacks.

Implementation language and scope

  • Written primarily in C.
  • Implements a functional RISC-V ISA simulator, executing instructions on a per-step basis without modeling detailed microarchitectural timing.
  • Acts as a reference implementation against which other RISC-V simulators are validated.

Comparison with other simulators

Spike is frequently compared with Swimmer-RISCV, another RISC-V instruction set simulator written in C++:

  • Spike is described in the Swimmer-RISCV documentation as a "very fast and simple RISC-V simulator written in C++" (the Swimmer-RISCV README characterizes Spike alongside Swimmer itself in a C++ context, while the GitHub metadata for riscv-isa-sim identifies the project's primary language as C).
  • Swimmer-RISCV, in contrast, emphasizes debugging-oriented features such as:
    • --debug, which logs register read/write and memory access activity.
    • --trace-hier, which produces a hierarchical function-call trace.
  • The two simulators can therefore be positioned as complements: Spike for high-throughput reference simulation, Swimmer-RISCV for detailed tracing and debugging of RISC-V binaries.

Repository statistics (as observed)

The public GitHub repository snapshot for riscv-isa-sim reports:

  • Stars: 3,165
  • Forks: 1,078
  • Primary language: C
  • Last updated: 2026-07-10

These figures indicate a large, actively maintained project with broad community adoption.

Usage context

Spike is commonly used as the reference model in the RISC-V software ecosystem, including for:

  • Running riscv-tests regression suites.
  • Cross-checking results from alternative simulators such as Swimmer-RISCV.
  • Booting RISC-V Linux binaries alongside a proxy kernel (pk).

Related entities

  • Instruction Set Simulator — generic concept implemented by Spike.
  • RISC-V — the instruction set architecture Spike implements.
  • Swimmer-RISCV — a debugging-oriented RISC-V ISS that is frequently compared with Spike.

LINKED ENTITIES

3 links
Instruction Set Simulator IMPLEMENTS
RISC-V IMPLEMENTS
Swimmer-RISCV COMPARES_WITH

CITATIONS

3 sources
3 citations
[1] Spike is the RISC-V ISA Simulator maintained by riscv-software-src on GitHub. riscv-software-src/riscv-isa-sim
[2] Spike is characterized as a very fast and simple RISC-V simulator and is used as a reference point when comparing with Swimmer-RISCV. msyksphinz-self/swimmer_riscv
[3] The riscv-isa-sim GitHub repository reports 3,165 stars, 1,078 forks, primary language C, and last updated 2026-07-10. riscv-software-src/riscv-isa-sim