MIPS

Concept

The provided evidence describes MIPS in the context of a GitHub project named Peggy-Gits/MIPS-CPU: a 5-stage pipelined MIPS processor implemented in SystemVerilog, with hazard handling and a UVM verification testbench that includes randomized instruction generation, monitoring, and coverage collection.

First seen 5/26/2026

Last seen 5/26/2026

Evidence 1 chunks

Wiki v1

WIKI

Overview

In the provided evidence, MIPS is represented by the Peggy-Gits/MIPS-CPU project, described as a 5-stage pipelined MIPS processor implemented in SystemVerilog. The processor is stated to support hazard handling.^[1]

Implementation

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NEIGHBORHOOD

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RELATIONSHIPS

1 connections

5-stage pipelined MIPS processor ← derived from 100% 1e

The 5-stage pipelined processor is based on the MIPS architecture.

LINKED ENTITIES

2 links

hazard handling has_capability The evidence states that the processor is capable of hazard handling.

UVM verification testbench verified_by The evidence states that the project contains a UVM verification testbench.

CITATIONS

3 sources

3 citations — click to collapse

[1] The Peggy-Gits/MIPS-CPU project is a 5-stage pipelined MIPS processor implemented with SystemVerilog. Peggy-Gits/MIPS-CPU

[2] The processor is capable of hazard handling. Peggy-Gits/MIPS-CPU

[3] The project contains a UVM verification testbench including a randomizing instruction generator, a monitor, and a coverage collector. Peggy-Gits/MIPS-CPU