5-stage pipelined MIPS processor

Concept

The **5-stage pipelined MIPS processor** is a SystemVerilog implementation of a MIPS CPU design using a five-stage pipeline architecture.[^1] The project includes hazard-handling capability and a verification environment based on UVM.[^1]

First seen 5/25/2026

Last seen 5/26/2026

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5-stage pipelined MIPS processor

The 5-stage pipelined MIPS processor is a SystemVerilog implementation of a MIPS CPU design using a five-stage pipeline architecture.^[1] The project includes hazard-handling capability and a verification environment based on UVM.^[1]

Overview

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RELATIONSHIPS

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MIPS-CPU ← implements 100% 1e

MIPS-CPU is a repository implementing a 5-stage pipelined MIPS processor.

MIPS derived from → 100% 1e

The 5-stage pipelined processor is based on the MIPS architecture.