MIPS-CPU

CodeArtifact

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First seen 5/25/2026

Last seen 5/26/2026

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MIPS-CPU

No evidence was provided for this CodeArtifact. As a result, implementation details, architecture, dependencies, behavior, usage, and relationships cannot be described without introducing unsupported claims.

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RELATIONSHIPS

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5-stage pipelined MIPS processor implements → 100% 1e

MIPS-CPU is a repository implementing a 5-stage pipelined MIPS processor.

SystemVerilog uses → 100% 1e

The MIPS-CPU project is implemented using SystemVerilog.

UVM verification testbench introduces → 100% 1e

The MIPS-CPU project includes a UVM verification testbench.