UVM verification testbench

Concept

A UVM verification testbench is documented in the Peggy-Gits/MIPS-CPU repository as part of a SystemVerilog project for a 5-stage pipelined MIPS processor. In that evidence, the testbench includes a randomizing instruction generator, a monitor, and a coverage collector.

First seen 5/26/2026

Last seen 5/26/2026

Evidence 1 chunks

Wiki v1

WIKI

Overview

In the available evidence, a UVM verification testbench appears as part of the Peggy-Gits/MIPS-CPU project. The repository describes the design under test as a 5-stage pipelined MIPS processor implemented in SystemVerilog and states that the processor is capable of hazard handling. [C1]

Testbench composition

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NEIGHBORHOOD

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RELATIONSHIPS

4 connections

MIPS-CPU ← introduces 100% 1e

The MIPS-CPU project includes a UVM verification testbench.

randomizing instruction generator ← part of 100% 1e

The UVM verification testbench includes a randomizing instruction generator.

monitor ← part of 100% 1e

The UVM verification testbench includes a monitor.

coverage collector ← part of 100% 1e

The UVM verification testbench includes a coverage collector.

LINKED ENTITIES

1 links

5-stage pipelined MIPS processor verifies_project_design The repository describes a 5-stage pipelined MIPS processor and states that the same project contains a UVM verification testbench.

CITATIONS

2 sources

2 citations — click to collapse

[1] The Peggy-Gits/MIPS-CPU project is a 5-stage pipelined MIPS processor implemented with SystemVerilog and capable of hazard handling. Peggy-Gits/MIPS-CPU

[2] The Peggy-Gits/MIPS-CPU project contains a UVM verification testbench including a randomizing instruction generator, a monitor, and a coverage collector. Peggy-Gits/MIPS-CPU