Clock Domain Crossing (CDC)

Concept

Clock Domain Crossing (CDC) refers to signal transfers between distinct asynchronous clock domains in digital designs, a common occurrence in modern System-on-Chip (SoC) designs that are prone to metastability effects and require specialized verification techniques.

First seen 7/11/2026

Last seen 7/11/2026

Evidence 2 chunks

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WIKI

Clock Domain Crossing (CDC)

Definition

A Clock Domain Crossing (CDC) occurs when a signal is transferred between two distinct clock domains in a digital design — that is, between flip-flops or logic elements clocked by different, asynchronous clocks. The term is most commonly used in the context of modern System-on-Chip (SoC) designs that operate on multiple asynchronous clock domains [arxiv:2406.06533v1].

Context in Modern SoC Designs

As SoC designs scale in complexity, designers often adopt a Globally-Asynchronous Locally-Synchronous (GALS) approach to improve power efficiency. In a GALS architecture, individual synchronous islands run on their own local clocks, while the boundaries between islands form asynchronous crossings. These crossings are the CDC paths, and their number grows with design complexity [arxiv:2406.06533v1].

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LINKED ENTITIES

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Clock Domain Crossing (CDC) self The article describes the concept itself.

System-on-Chip (SoC) context The public context situates CDC within modern SoC design complexity.

SystemVerilog Assertions (SVA) related SVA is referenced in the OpenTitan evidence as the mechanism used to check CDC handshake and clock-enable properties.

CITATIONS

7 sources

7 citations — click to expand

[1] Modern SoC designs often operate on multiple asynchronous clock domains, and the GALS approach creates multiple asynchronous domains. Pragmatic Formal Verification Methodology for Clock Domain Crossing (CDC)

[2] CDC paths are prone to metastability effects, and functional verification of CDC is important to ensure no bug escapes. Pragmatic Formal Verification Methodology for Clock Domain Crossing (CDC)

[3] Conventional verification methods (RTL simulation and STA) are not sufficient to address CDC issues and may lead to verification gaps. Pragmatic Formal Verification Methodology for Clock Domain Crossing (CDC)

[4] Identifying CDC-related bugs is time-consuming and one of the most common reasons for costly silicon re-spins. Pragmatic Formal Verification Methodology for Clock Domain Crossing (CDC)

[5] A pragmatic formal verification methodology exercises Metastability Injection (MSI) in different CDC paths to minimize CDC issues. Pragmatic Formal Verification Methodology for Clock Domain Crossing (CDC)

[6] In the OpenTitan pwrmgr, a CSR clearing indicates that the CDC to the slow clock has completed. Design Verification - OpenTitan Documentation

[7] Clock enable handshakes between slow and fast domains in pwrmgr are driven by slow_responder / fast_responder and checked via SVA files such as pwrmgr_clock_enables_sva_if.sv and pwrmgr_ast_sva_if.sv. Design Verification - OpenTitan Documentation