AXI4-Lite Protocol

Concept

AXI4-Lite is an interface protocol used in hardware/IC designs. It is one of three interface protocols (Direct, Wishbone, AXI4-Lite) supported by the HAVEN tool for automated UVM testbench synthesis.

First seen 7/12/2026

Last seen 7/12/2026

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AXI4-Lite Protocol

Overview

AXI4-Lite is an on-chip bus interface protocol used for register-style access in hardware designs. It is mentioned in the context of LLM-assisted UVM (Universal Verification Methodology) testbench generation.

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RELATIONSHIPS

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HAVEN ← evaluates 93% 1e

HAVEN is evaluated on IP designs using AXI4-Lite interface protocol.

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HAVEN EVALUATES Extracted graph relationship

CITATIONS

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[1] AXI4-Lite is one of three interface protocols (Direct, Wishbone, AXI4-Lite) supported by HAVEN. HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs

[2] HAVEN was evaluated on 19 open-source IP designs (180-11k LOC) spanning AXI4-Lite among other protocols. HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs

[3] HAVEN achieves 100% compilation success, 90.6% code coverage, and 87.9% functional coverage on average across designs including AXI4-Lite. HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs

[4] HAVEN uses predefined, protocol-specific Jinja2 templates to generate UVM components and a Protocol-Aware Sequence DSL for sequences. HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs