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AXI4-Lite Protocol

Concept WIKI v1 · 7/12/2026

AXI4-Lite is an interface protocol used in hardware/IC designs. It is one of three interface protocols (Direct, Wishbone, AXI4-Lite) supported by the HAVEN tool for automated UVM testbench synthesis.

AXI4-Lite Protocol

Overview

AXI4-Lite is an on-chip bus interface protocol used for register-style access in hardware designs. It is mentioned in the context of LLM-assisted UVM (Universal Verification Methodology) testbench generation.

Role in HAVEN Evaluation

AXI4-Lite is one of three interface protocols evaluated by HAVEN (Hybrid Automated Verification ENgine), alongside Direct and Wishbone.

In HAVEN's experimental setup:

  • The tool was tested on 19 open-source IP designs ranging from 180 to 11k lines of code (LOC).
  • These designs spanned three interface protocols: Direct, Wishbone, and AXI4-Lite.
  • HAVEN uses predefined, protocol-specific Jinja2 templates to generate UVM components and sequences, with a Protocol-Aware Sequence DSL that decomposes sequences into fine-grained step types.

Results

On the AXI4-Lite designs (among others), HAVEN achieved:

  • 100% compilation success
  • 90.6% code coverage (on average)
  • 87.9% functional coverage (on average)

These results position HAVEN as state-of-the-art (SOTA) among LLM-assisted testbench generation systems that support the AXI4-Lite protocol.

Notes

The available evidence characterizes AXI4-Lite solely as a supported interface protocol in HAVEN's evaluation. Detailed timing, signal-level, or transaction-level specifications of the AXI4-Lite protocol itself are not provided in the source material.

LINKED ENTITIES

1 links
HAVEN EVALUATES

CITATIONS

4 sources
4 citations
[1] AXI4-Lite is one of three interface protocols (Direct, Wishbone, AXI4-Lite) supported by HAVEN. HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs
[2] HAVEN was evaluated on 19 open-source IP designs (180-11k LOC) spanning AXI4-Lite among other protocols. HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs
[3] HAVEN achieves 100% compilation success, 90.6% code coverage, and 87.9% functional coverage on average across designs including AXI4-Lite. HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs
[4] HAVEN uses predefined, protocol-specific Jinja2 templates to generate UVM components and a Protocol-Aware Sequence DSL for sequences. HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs