2026-07-13
4 items 158 entities 205 connections
An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor
source →Processed 55 entities and 65 relations.
An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor Idris O. Somoye Jim Plusquellic Tom J. Mannos Brian Dziki University of New Mexico Sandia National Laboratories Department of Defense Periodic Built-In-Self-Test information leakage fault fault detection severe fault fault propagation latency Automatic Test Pattern Generation counter-based node monitoring Fault Trigger Binary Executable Fault-Run-Cycle-Based FTBE ATPG-Based FTBE processor state replication Incremental Fault-Triggered Cycle Binary Search Fault-Detected Cycle fault injection scan chain stuck-at fault delay fault inversion fault TopCounters Fault Injection Manager Fault Emulation Engine Emulation ROM Side Loading PODEM Yosys Fault (open-source DFT toolchain) Synopsys Design Compiler RISC-V online assembler SystemVerilog testbench RISC-V RV32I Potato RISC-V processor Advanced Encryption Standard Self-Assertion-Based Countermeasures Dynamic Implementation Verification Architecture Access-Control Extension RTL Design for Testability FPGA emulation Xilinx UltraScale+ MPSoC ZCU102 Wishbone bus binary program ASAP7 standard cell library osu035 standard cell library Coremark benchmark Fault-Run-Cycle-Based FTBE ATPG-Based FTBE Fault Trigger Binary Executable
Processed 44 entities and 59 relations.
Encarsia: Evaluating CPU Fuzzers via Automatic Bug Injection Matej Bölcskei Flavien Solt Katharina Ceesay-Seitz Kaveh Razavi ETH Zurich ENCARSIA hardware fuzzing bug injection signal mix-up broken conditional RTL RISC-V DifuzzRTL ProcessorFuzz Cascade Ibex CVA6 Rocket BOOM Yosys RTLIL multiplexer tree formal verification JasperGold coverage metric ISA simulator differential fuzzing EnCorpus SystemVerilog Assertions assume-guarantee reasoning seed program RFUZZ control register coverage multiplexer select coverage ISA coverage intermediate representation HDL design under test manual bug insertion HACK@DAC competition mutation-based fuzzing false positive elimination ENCARSIA
Processed 26 entities and 33 relations.
SystemC Verification Library SystemC Constraint-based Randomization Random Pattern Simulation Directed Simulation Binary Decision Diagram Uniform Distribution of Constraint Solutions Bit Operators in SCV Constraints BDD Weighting Algorithm Constraint Solver Simulation-based Verification Functional Coverage CUDD scv_constraint_base scv_expression scv_smart_ptr scv_constraint_manager Daniel Große Rudiger Ebendt Rolf Drechsler University of Bremen German Aerospace Center Improvements for Constraint Solving in the SystemC Verification Library Complement Edges in BDD Transaction Recording Data Introspection
Processed 33 entities and 48 relations.
Constraint-based Random Simulation Contradiction Analysis Stimulus Generation Directed Simulation Constraint Solving Binary Decision Diagrams Existential Quantification Unsat Core Computation Formal Verification Design Verification SCV Library CUDD BDD Package SystemC SystemVerilog Over-constraining Corner Case Test Scenarios Constraint Contradiction Minimal Unsatisfiable Subformula Boolean Satisfiability System-on-Chip PCIe Transaction Generator Bus Functional Model Random Constraint Verification SCV_CONSTRAINT Macro ContradictionAnalysis Algorithm Daniel Große Robert Wille Robert Siegmund Rolf Drechsler University of Bremen AMD Saxony LLC Contradiction Analysis for Constraint-based Random Simulation Design Verification